1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14 [--help] [-I dir] [-J]
15 [-K] [-L] [--listing-lhs-width=NUM]
16 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17 [--listing-cont-lines=NUM] [--keep-locals]
18 [--no-pad-sections]
19 [-o objfile] [-R]
20 [--hash-size=NUM] [--reduce-memory-overheads]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--generate-missing-build-notes=[no|yes]]
28 [--target-help] [target-options]
29 [--|files ...]
30
32 Target AArch64 options:
33 [-EB|-EL]
34 [-mabi=ABI]
35 Target Alpha options:
37 [-mcpu]
38 [-mdebug | -no-mdebug]
39 [-replace | -noreplace]
40 [-relax] [-g] [-Gsize]
41 [-F] [-32addr]
42 Target ARC options:
44 [-mcpu=cpu]
45 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
46 [-mcode-density]
47 [-mrelax]
48 [-EB|-EL]
49 Target ARM options:
51 [-mcpu=processor[+extension...]]
52 [-march=architecture[+extension...]]
53 [-mfpu=floating-point-format]
54 [-mfloat-abi=abi]
55 [-meabi=ver]
56 [-mthumb]
57 [-EB|-EL]
58 [-mapcs-32|-mapcs-26|-mapcs-float|
59 -mapcs-reentrant]
60 [-mthumb-interwork] [-k]
61 Target Blackfin options:
63 [-mcpu=processor[-sirevision]]
64 [-mfdpic]
65 [-mno-fdpic]
66 [-mnopic]
67 Target CRIS options:
69 [--underscore | --no-underscore]
70 [--pic] [-N]
71 [--emulation=criself | --emulation=crisaout]
72 [--march=v0_v10 | --march=v10 | --march=v32 |
73 --march=common_v10_v32]
74 Target D10V options:
76 [-O]
77 Target D30V options:
79 [-O|-n|-N]
80 Target EPIPHANY options:
82 [-mepiphany|-mepiphany16]
83 Target H8/300 options:
85 [-h-tick-hex]
86 Target i386 options:
88 [--32|--x32|--64] [-n]
89 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
90 Target IA-64 options:
92 [-mconstant-gp|-mauto-pic]
93 [-milp32|-milp64|-mlp64|-mp64]
94 [-mle|mbe]
95 [-mtune=itanium1|-mtune=itanium2]
96 [-munwind-check=warning|-munwind-check=error]
97 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
98 [-x|-xexplicit] [-xauto] [-xdebug]
99 Target IP2K options:
101 [-mip2022|-mip2022ext]
102 Target M32C options:
104 [-m32c|-m16c] [-relax] [-h-tick-hex]
105 Target M32R options:
107 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
108 --W[n]p]
109 Target M680X0 options:
111 [-l] [-m68000|-m68010|-m68020|...]
112 Target M68HC11 options:
114 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
115 [-mshort|-mlong]
116 [-mshort-double|-mlong-double]
117 [--force-long-branches] [--short-branches]
118 [--strict-direct-mode] [--print-insn-syntax]
119 [--print-opcodes] [--generate-example]
120 Target MCORE options:
122 [-jsri2bsr] [-sifilter] [-relax]
123 [-mcpu=[210|340]]
124 Target Meta options:
126 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
127 Target MIPS options:
129 [-nocpp] [-EL] [-EB] [-O[optimization level]]
130 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
131 [-non_shared] [-xgot [-mvxworks-pic]
132 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
133 [-mfp64] [-mgp64] [-mfpxx]
134 [-modd-spreg] [-mno-odd-spreg]
135 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
136 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
137 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
138 [-mips64r3] [-mips64r5] [-mips64r6]
139 [-construct-floats] [-no-construct-floats]
140 [-mignore-branch-isa] [-mno-ignore-branch-isa]
141 [-mnan=encoding]
142 [-trap] [-no-break] [-break] [-no-trap]
143 [-mips16] [-no-mips16]
144 [-mmips16e2] [-mno-mips16e2]
145 [-mmicromips] [-mno-micromips]
146 [-msmartmips] [-mno-smartmips]
147 [-mips3d] [-no-mips3d]
148 [-mdmx] [-no-mdmx]
149 [-mdsp] [-mno-dsp]
150 [-mdspr2] [-mno-dspr2]
151 [-mdspr3] [-mno-dspr3]
152 [-mmsa] [-mno-msa]
153 [-mxpa] [-mno-xpa]
154 [-mmt] [-mno-mt]
155 [-mmcu] [-mno-mcu]
156 [-mcrc] [-mno-crc]
157 [-mginv] [-mno-ginv]
158 [-minsn32] [-mno-insn32]
159 [-mfix7000] [-mno-fix7000]
160 [-mfix-rm7000] [-mno-fix-rm7000]
161 [-mfix-vr4120] [-mno-fix-vr4120]
162 [-mfix-vr4130] [-mno-fix-vr4130]
163 [-mdebug] [-no-mdebug]
164 [-mpdr] [-mno-pdr]
165 Target MMIX options:
167 [--fixed-special-register-names] [--globalize-symbols]
168 [--gnu-syntax] [--relax] [--no-predefined-symbols]
169 [--no-expand] [--no-merge-gregs] [-x]
170 [--linker-allocated-gregs]
171 Target Nios II options:
173 [-relax-all] [-relax-section] [-no-relax]
174 [-EB] [-EL]
175 Target NDS32 options:
177 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
178 [-misa=isa] [-mabi=abi] [-mall-ext]
179 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
180 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
181 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
182 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
183 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
184 [-mb2bb]
185 Target PDP11 options:
187 [-mpic|-mno-pic] [-mall] [-mno-extensions]
188 [-mextension|-mno-extension]
189 [-mcpu] [-mmachine]
190 Target picoJava options:
192 [-mb|-me]
193 Target PowerPC options:
195 [-a32|-a64]
196 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
197 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
198 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
199 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
200 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
201 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
202 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
203 [-mregnames|-mno-regnames]
204 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
205 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
206 [-msolaris|-mno-solaris]
207 [-nops=count]
208 Target PRU options:
210 [-link-relax]
211 [-mnolink-relax]
212 [-mno-warn-regname-label]
213 Target RISC-V options:
215 [-fpic|-fPIC|-fno-pic]
216 [-march=ISA]
217 [-mabi=ABI]
218 Target RL78 options:
220 [-mg10]
221 [-m32bit-doubles|-m64bit-doubles]
222 Target RX options:
224 [-mlittle-endian|-mbig-endian]
225 [-m32bit-doubles|-m64bit-doubles]
226 [-muse-conventional-section-names]
227 [-msmall-data-limit]
228 [-mpid]
229 [-mrelax]
230 [-mint-register=number]
231 [-mgcc-abi|-mrx-abi]
232 Target s390 options:
234 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
235 [-mregnames|-mno-regnames]
236 [-mwarn-areg-zero]
237 Target SCORE options:
239 [-EB][-EL][-FIXDD][-NWARN]
240 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
241 [-march=score7][-march=score3]
242 [-USE_R1][-KPIC][-O0][-G num][-V]
243 Target SPARC options:
245 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
246 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
247 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
248 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
249 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
250 -Asparcvisr|-Asparc5]
251 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
252 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
253 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
254 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
255 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
256 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
257 -bump]
258 [-32|-64]
259 [--enforce-aligned-data][--dcti-couples-detect]
260 Target TIC54X options:
262 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
263 [-merrors-to-file <filename>|-me <filename>]
264 Target TIC6X options:
266 [-march=arch] [-mbig-endian|-mlittle-endian]
267 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
268 [-mpic|-mno-pic]
269 Target TILE-Gx options:
271 [-m32|-m64][-EB][-EL]
272 Target Visium options:
274 [-mtune=arch]
275 Target Xtensa options:
277 [--[no-]text-section-literals] [--[no-]auto-litpools]
278 [--[no-]absolute-literals]
279 [--[no-]target-align] [--[no-]longcalls]
280 [--[no-]transform]
281 [--rename-section oldname=newname]
282 [--[no-]trampolines]
283 Target Z80 options:
285 [-z80] [-r800]
286 [ -ignore-undocumented-instructions] [-Wnud]
287 [ -ignore-unportable-instructions] [-Wnup]
288 [ -warn-undocumented-instructions] [-Wud]
289 [ -warn-unportable-instructions] [-Wup]
290 [ -forbid-undocumented-instructions] [-Fud]
291 [ -forbid-unportable-instructions] [-Fup]
292
294 GNU as is really a family of assemblers. If you use (or have used) the
295 GNU assembler on one architecture, you should find a fairly similar
296 environment when you use it on another architecture. Each version has
297 much in common with the others, including object file formats, most
298 assembler directives (often called pseudo-ops) and assembler syntax.
299 as is primarily intended to assemble the output of the GNU C compiler
301 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
302 assemble correctly everything that other assemblers for the same
303 machine would assemble. Any exceptions are documented explicitly.
304 This doesn't mean as always uses the same syntax as another assembler
305 for the same architecture; for example, we know of several incompatible
306 versions of 680x0 assembly language syntax.
307 Each time you run as it assembles exactly one source program. The
309 source program is made up of one or more files. (The standard input is
310 also a file.)
311 You give as a command line that has zero or more input file names. The
313 input files are read (from left file name to right). A command line
314 argument (in any position) that has no special meaning is taken to be
315 an input file name.
316 If you give as no file names it attempts to read one input file from
318 the as standard input, which is normally your terminal. You may have
319 to type ctl-D to tell as there is no more program to assemble.
320 Use -- if you need to explicitly name the standard input file in your
322 command line.
323 If the source is empty, as produces a small, empty object file.
325 as may write warnings and error messages to the standard error file
327 (usually your terminal). This should not happen when a compiler runs
328 as automatically. Warnings report an assumption made so that as could
329 keep assembling a flawed program; errors report a grave problem that
330 stops the assembly.
331 If you are invoking as via the GNU C compiler, you can use the -Wa
333 option to pass arguments through to the assembler. The assembler
334 arguments must be separated from each other (and the -Wa) by commas.
335 For example:
336 gcc -c -g -O -Wa,-alh,-L file.c
338 This passes two options to the assembler: -alh (emit a listing to
340 standard output with high-level and assembly source) and -L (retain
341 local symbols in the symbol table).
342 Usually you do not need to use this -Wa mechanism, since many compiler
344 command-line options are automatically passed to the assembler by the
345 compiler. (You can call the GNU compiler driver with the -v option to
346 see precisely what options it passes to each compilation pass,
347 including the assembler.)
348
350 @file
351 Read command-line options from file. The options read are inserted
352 in place of the original @file option. If file does not exist, or
353 cannot be read, then the option will be treated literally, and not
354 removed.
355 Options in file are separated by whitespace. A whitespace
357 character may be included in an option by surrounding the entire
358 option in either single or double quotes. Any character (including
359 a backslash) may be included by prefixing the character to be
360 included with a backslash. The file may itself contain additional
361 @file options; any such options will be processed recursively.
362 -a[cdghlmns]
364 Turn on listings, in any of a variety of ways:
365 -ac omit false conditionals
367 -ad omit debugging directives
369 -ag include general information, like as version and options passed
371 -ah include high-level source
373 -al include assembly
375 -am include macro expansions
377 -an omit forms processing
379 -as include symbols
381 =file
383 set the name of the listing file
384 You may combine these options; for example, use -aln for assembly
386 listing without forms processing. The =file option, if used, must
387 be the last one. By itself, -a defaults to -ahls.
388 --alternate
390 Begin in alternate macro mode.
391 --compress-debug-sections
393 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
394 the ELF ABI. The resulting object file may not be compatible with
395 older linkers and object file utilities. Note if compression would
396 make a given section larger then it is not compressed.
397 --compress-debug-sections=none
399 --compress-debug-sections=zlib
400 --compress-debug-sections=zlib-gnu
401 --compress-debug-sections=zlib-gabi
402 These options control how DWARF debug sections are compressed.
403 --compress-debug-sections=none is equivalent to
404 --nocompress-debug-sections. --compress-debug-sections=zlib and
405 --compress-debug-sections=zlib-gabi are equivalent to
406 --compress-debug-sections. --compress-debug-sections=zlib-gnu
407 compresses DWARF debug sections using zlib. The debug sections are
408 renamed to begin with .zdebug. Note if compression would make a
409 given section larger then it is not compressed nor renamed.
410 --nocompress-debug-sections
412 Do not compress DWARF debug sections. This is usually the default
413 for all targets except the x86/x86_64, but a configure time option
414 can be used to override this.
415 -D Ignored. This option is accepted for script compatibility with
417 calls to other assemblers.
418 --debug-prefix-map old=new
420 When assembling files in directory old, record debugging
421 information describing them as in new instead.
422 --defsym sym=value
424 Define the symbol sym to be value before assembling the input file.
425 value must be an integer constant. As in C, a leading 0x indicates
426 a hexadecimal value, and a leading 0 indicates an octal value. The
427 value of the symbol can be overridden inside a source file via the
428 use of a ".set" pseudo-op.
429 -f "fast"---skip whitespace and comment preprocessing (assume source
431 is compiler output).
432 -g
434 --gen-debug
435 Generate debugging information for each assembler source line using
436 whichever debug format is preferred by the target. This currently
437 means either STABS, ECOFF or DWARF2.
438 --gstabs
440 Generate stabs debugging information for each assembler line. This
441 may help debugging assembler code, if the debugger can handle it.
442 --gstabs+
444 Generate stabs debugging information for each assembler line, with
445 GNU extensions that probably only gdb can handle, and that could
446 make other debuggers crash or refuse to read your program. This
447 may help debugging assembler code. Currently the only GNU
448 extension is the location of the current working directory at
449 assembling time.
450 --gdwarf-2
452 Generate DWARF2 debugging information for each assembler line.
453 This may help debugging assembler code, if the debugger can handle
454 it. Note---this option is only supported by some targets, not all
455 of them.
456 --gdwarf-sections
458 Instead of creating a .debug_line section, create a series of
459 .debug_line.foo sections where foo is the name of the corresponding
460 code section. For example a code section called .text.func will
461 have its dwarf line number information placed into a section called
462 .debug_line.text.func. If the code section is just called .text
463 then debug line section will still be called just .debug_line
464 without any suffix.
465 --size-check=error
467 --size-check=warning
468 Issue an error or warning for invalid ELF .size directive.
469 --elf-stt-common=no
471 --elf-stt-common=yes
472 These options control whether the ELF assembler should generate
473 common symbols with the "STT_COMMON" type. The default can be
474 controlled by a configure option --enable-elf-stt-common.
475 --generate-missing-build-notes=yes
477 --generate-missing-build-notes=no
478 These options control whether the ELF assembler should generate GNU
479 Build attribute notes if none are present in the input sources.
480 The default can be controlled by the --enable-generate-build-notes
481 configure option.
482 --help
484 Print a summary of the command line options and exit.
485 --target-help
487 Print a summary of all target specific options and exit.
488 -I dir
490 Add directory dir to the search list for ".include" directives.
491 -J Don't warn about signed overflow.
493 -K Issue warnings when difference tables altered for long
495 displacements.
496 -L
498 --keep-locals
499 Keep (in the symbol table) local symbols. These symbols start with
500 system-specific local label prefixes, typically .L for ELF systems
501 or L for traditional a.out systems.
502 --listing-lhs-width=number
504 Set the maximum width, in words, of the output data column for an
505 assembler listing to number.
506 --listing-lhs-width2=number
508 Set the maximum width, in words, of the output data column for
509 continuation lines in an assembler listing to number.
510 --listing-rhs-width=number
512 Set the maximum width of an input source line, as displayed in a
513 listing, to number bytes.
514 --listing-cont-lines=number
516 Set the maximum number of lines printed in a listing for a single
517 line of input to number + 1.
518 --no-pad-sections
520 Stop the assembler for padding the ends of output sections to the
521 alignment of that section. The default is to pad the sections, but
522 this can waste space which might be needed on targets which have
523 tight memory constraints.
524 -o objfile
526 Name the object-file output from as objfile.
527 -R Fold the data section into the text section.
529 --hash-size=number
531 Set the default size of GAS's hash tables to a prime number close
532 to number. Increasing this value can reduce the length of time it
533 takes the assembler to perform its tasks, at the expense of
534 increasing the assembler's memory requirements. Similarly reducing
535 this value can reduce the memory requirements at the expense of
536 speed.
537 --reduce-memory-overheads
539 This option reduces GAS's memory requirements, at the expense of
540 making the assembly processes slower. Currently this switch is a
541 synonym for --hash-size=4051, but in the future it may have other
542 effects as well.
543 --sectname-subst
545 Honor substitution sequences in section names.
546 --statistics
548 Print the maximum space (in bytes) and total time (in seconds) used
549 by assembly.
550 --strip-local-absolute
552 Remove local absolute symbols from the outgoing symbol table.
553 -v
555 -version
556 Print the as version.
557 --version
559 Print the as version and exit.
560 -W
562 --no-warn
563 Suppress warning messages.
564 --fatal-warnings
566 Treat warnings as errors.
567 --warn
569 Don't suppress warning messages or treat them as errors.
570 -w Ignored.
572 -x Ignored.
574 -Z Generate an object file even after errors.
576 -- | files ...
578 Standard input, or source files to assemble.
579 The following options are available when as is configured for the
581 64-bit mode of the ARM Architecture (AArch64).
582 -EB This option specifies that the output generated by the assembler
584 should be marked as being encoded for a big-endian processor.
585 -EL This option specifies that the output generated by the assembler
587 should be marked as being encoded for a little-endian processor.
588 -mabi=abi
590 Specify which ABI the source code uses. The recognized arguments
591 are: "ilp32" and "lp64", which decides the generated object file in
592 ELF32 and ELF64 format respectively. The default is "lp64".
593 -mcpu=processor[+extension...]
595 This option specifies the target processor. The assembler will
596 issue an error message if an attempt is made to assemble an
597 instruction which will not execute on the target processor. The
598 following processor names are recognized: "cortex-a35",
599 "cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72",
600 "cortex-a73", "cortex-a75", "cortex-a76", "exynos-m1", "falkor",
601 "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1" and "xgene2".
602 The special name "all" may be used to allow the assembler to accept
603 instructions valid for any supported processor, including all
604 optional extensions.
605 In addition to the basic instruction set, the assembler can be told
607 to accept, or restrict, various extension mnemonics that extend the
608 processor.
609 If some implementations of a particular processor can have an
611 extension, then then those extensions are automatically enabled.
612 Consequently, you will not normally have to specify any additional
613 extensions.
614 -march=architecture[+extension...]
616 This option specifies the target architecture. The assembler will
617 issue an error message if an attempt is made to assemble an
618 instruction which will not execute on the target architecture. The
619 following architecture names are recognized: "armv8-a",
620 "armv8.1-a", "armv8.2-a", "armv8.3-a" and "armv8.4-a".
621 If both -mcpu and -march are specified, the assembler will use the
623 setting for -mcpu. If neither are specified, the assembler will
624 default to -mcpu=all.
625 The architecture option can be extended with the same instruction
627 set extension options as the -mcpu option. Unlike -mcpu,
628 extensions are not always enabled by default,
629 -mverbose-error
631 This option enables verbose error messages for AArch64 gas. This
632 option is enabled by default.
633 -mno-verbose-error
635 This option disables verbose error messages in AArch64 gas.
636 The following options are available when as is configured for an Alpha
638 processor.
639 -mcpu
641 This option specifies the target processor. If an attempt is made
642 to assemble an instruction which will not execute on the target
643 processor, the assembler may either expand the instruction as a
644 macro or issue an error message. This option is equivalent to the
645 ".arch" directive.
646 The following processor names are recognized: 21064, "21064a",
648 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
649 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
650 "ev67", "ev68". The special name "all" may be used to allow the
651 assembler to accept instructions valid for any Alpha processor.
652 In order to support existing practice in OSF/1 with respect to
654 ".arch", and existing practice within MILO (the Linux ARC
655 bootloader), the numbered processor names (e.g. 21064) enable the
656 processor-specific PALcode instructions, while the "electro-vlasic"
657 names (e.g. "ev4") do not.
658 -mdebug
660 -no-mdebug
661 Enables or disables the generation of ".mdebug" encapsulation for
662 stabs directives and procedure descriptors. The default is to
663 automatically enable ".mdebug" when the first stabs directive is
664 seen.
665 -relax
667 This option forces all relocations to be put into the object file,
668 instead of saving space and resolving some relocations at assembly
669 time. Note that this option does not propagate all symbol
670 arithmetic into the object file, because not all symbol arithmetic
671 can be represented. However, the option can still be useful in
672 specific applications.
673 -replace
675 -noreplace
676 Enables or disables the optimization of procedure calls, both at
677 assemblage and at link time. These options are only available for
678 VMS targets and "-replace" is the default. See section 1.4.1 of
679 the OpenVMS Linker Utility Manual.
680 -g This option is used when the compiler generates debug information.
682 When gcc is using mips-tfile to generate debug information for
683 ECOFF, local labels must be passed through to the object file.
684 Otherwise this option has no effect.
685 -Gsize
687 A local common symbol larger than size is placed in ".bss", while
688 smaller symbols are placed in ".sbss".
689 -F
691 -32addr
692 These options are ignored for backward compatibility.
693 The following options are available when as is configured for an ARC
695 processor.
696 -mcpu=cpu
698 This option selects the core processor variant.
699 -EB | -EL
701 Select either big-endian (-EB) or little-endian (-EL) output.
702 -mcode-density
704 Enable Code Density extenssion instructions.
705 The following options are available when as is configured for the ARM
707 processor family.
708 -mcpu=processor[+extension...]
710 Specify which ARM processor variant is the target.
711 -march=architecture[+extension...]
713 Specify which ARM architecture variant is used by the target.
714 -mfpu=floating-point-format
716 Select which Floating Point architecture is the target.
717 -mfloat-abi=abi
719 Select which floating point ABI is in use.
720 -mthumb
722 Enable Thumb only instruction decoding.
723 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
725 Select which procedure calling convention is in use.
726 -EB | -EL
728 Select either big-endian (-EB) or little-endian (-EL) output.
729 -mthumb-interwork
731 Specify that the code has been generated with interworking between
732 Thumb and ARM code in mind.
733 -mccs
735 Turns on CodeComposer Studio assembly syntax compatibility mode.
736 -k Specify that PIC code has been generated.
738 The following options are available when as is configured for the
740 Blackfin processor family.
741 -mcpu=processor[-sirevision]
743 This option specifies the target processor. The optional
744 sirevision is not used in assembler. It's here such that GCC can
745 easily pass down its "-mcpu=" option. The assembler will issue an
746 error message if an attempt is made to assemble an instruction
747 which will not execute on the target processor. The following
748 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
749 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
750 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
751 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
752 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
753 "bf549", "bf549m", "bf561", and "bf592".
754 -mfdpic
756 Assemble for the FDPIC ABI.
757 -mno-fdpic
759 -mnopic
760 Disable -mfdpic.
761 See the info pages for documentation of the CRIS-specific options.
763 The following options are available when as is configured for a D10V
765 processor.
766 -O Optimize output by parallelizing instructions.
768 The following options are available when as is configured for a D30V
770 processor.
771 -O Optimize output by parallelizing instructions.
773 -n Warn when nops are generated.
775 -N Warn when a nop after a 32-bit multiply instruction is generated.
777 The following options are available when as is configured for an
779 Epiphany processor.
780 -mepiphany
782 Specifies that the both 32 and 16 bit instructions are allowed.
783 This is the default behavior.
784 -mepiphany16
786 Restricts the permitted instructions to just the 16 bit set.
787 The following options are available when as is configured for an H8/300
789 processor. @chapter H8/300 Dependent Features
790 Options
792 The Renesas H8/300 version of "as" has one machine-dependent option:
793 -h-tick-hex
795 Support H'00 style hex constants in addition to 0x00 style.
796 -mach=name
798 Sets the H8300 machine variant. The following machine names are
799 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
800 "h8300sxn".
801 The following options are available when as is configured for an i386
803 processor.
804 --32 | --x32 | --64
806 Select the word size, either 32 bits or 64 bits. --32 implies
807 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
808 architecture with 32-bit or 64-bit word-size respectively.
809 These options are only available with the ELF object file format,
811 and require that the necessary BFD support has been included (on a
812 32-bit platform you have to add --enable-64-bit-bfd to configure
813 enable 64-bit usage and use x86-64 as target platform).
814 -n By default, x86 GAS replaces multiple nop instructions used for
816 alignment within code sections with multi-byte nop instructions
817 such as leal 0(%esi,1),%esi. This switch disables the optimization
818 if a single byte nop (0x90) is explicitly specified as the fill
819 byte for alignment.
820 --divide
822 On SVR4-derived platforms, the character / is treated as a comment
823 character, which means that it cannot be used in expressions. The
824 --divide option turns / into a normal character. This does not
825 disable / at the beginning of a line starting a comment, or affect
826 using # for starting a comment.
827 -march=CPU[+EXTENSION...]
829 This option specifies the target processor. The assembler will
830 issue an error message if an attempt is made to assemble an
831 instruction which will not execute on the target processor. The
832 following processor names are recognized: "i8086", "i186", "i286",
833 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
834 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
835 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
836 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
837 "bdver3", "bdver4", "znver1", "znver2", "btver1", "btver2",
838 "generic32" and "generic64".
839 In addition to the basic instruction set, the assembler can be told
841 to accept various extension mnemonics. For example,
842 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
843 following extensions are currently supported: 8087, 287, 387, 687,
844 "no87", "no287", "no387", "no687", "mmx", "nommx", "sse", "sse2",
845 "sse3", "ssse3", "sse4.1", "sse4.2", "sse4", "nosse", "nosse2",
846 "nosse3", "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx",
847 "avx2", "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap",
848 "mpx", "sha", "rdpid", "ptwrite", "cet", "gfni", "vaes",
849 "vpclmulqdq", "prefetchwt1", "clflushopt", "se1", "clwb",
850 "movdiri", "movdir64b", "avx512f", "avx512cd", "avx512er",
851 "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma",
852 "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
853 "avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "noavx512f",
854 "noavx512cd", "noavx512er", "noavx512pf", "noavx512vl",
855 "noavx512bw", "noavx512dq", "noavx512ifma", "noavx512vbmi",
856 "noavx512_4fmaps", "noavx512_4vnniw", "noavx512_vpopcntdq",
857 "noavx512_vbmi2", "noavx512_vnni", "noavx512_bitalg", "vmx",
858 "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes",
859 "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe",
860 "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx",
861 "clzero", "wbnoinvd", "pconfig", "waitpkg", "cldemote", "lwp",
862 "fma4", "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa",
863 "sse4a", "sse5", "svme", "abm" and "padlock". Note that rather
864 than extending a basic instruction set, the extension mnemonics
865 starting with "no" revoke the respective functionality.
866 When the ".arch" directive is used with -march, the ".arch"
868 directive will take precedent.
869 -mtune=CPU
871 This option specifies a processor to optimize for. When used in
872 conjunction with the -march option, only instructions of the
873 processor specified by the -march option will be generated.
874 Valid CPU values are identical to the processor list of -march=CPU.
876 -msse2avx
878 This option specifies that the assembler should encode SSE
879 instructions with VEX prefix.
880 -msse-check=none
882 -msse-check=warning
883 -msse-check=error
884 These options control if the assembler should check SSE
885 instructions. -msse-check=none will make the assembler not to
886 check SSE instructions, which is the default. -msse-check=warning
887 will make the assembler issue a warning for any SSE instruction.
888 -msse-check=error will make the assembler issue an error for any
889 SSE instruction.
890 -mavxscalar=128
892 -mavxscalar=256
893 These options control how the assembler should encode scalar AVX
894 instructions. -mavxscalar=128 will encode scalar AVX instructions
895 with 128bit vector length, which is the default. -mavxscalar=256
896 will encode scalar AVX instructions with 256bit vector length.
897 -mevexlig=128
899 -mevexlig=256
900 -mevexlig=512
901 These options control how the assembler should encode length-
902 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
903 EVEX instructions with 128bit vector length, which is the default.
904 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
905 with 256bit and 512bit vector length, respectively.
906 -mevexwig=0
908 -mevexwig=1
909 These options control how the assembler should encode w-ignored
910 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
911 instructions with evex.w = 0, which is the default. -mevexwig=1
912 will encode WIG EVEX instructions with evex.w = 1.
913 -mmnemonic=att
915 -mmnemonic=intel
916 This option specifies instruction mnemonic for matching
917 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
918 will take precedent.
919 -msyntax=att
921 -msyntax=intel
922 This option specifies instruction syntax when processing
923 instructions. The ".att_syntax" and ".intel_syntax" directives
924 will take precedent.
925 -mnaked-reg
927 This option specifies that registers don't require a % prefix. The
928 ".att_syntax" and ".intel_syntax" directives will take precedent.
929 -madd-bnd-prefix
931 This option forces the assembler to add BND prefix to all branches,
932 even if such prefix was not explicitly specified in the source
933 code.
934 -mno-shared
936 On ELF target, the assembler normally optimizes out non-PLT
937 relocations against defined non-weak global branch targets with
938 default visibility. The -mshared option tells the assembler to
939 generate code which may go into a shared library where all non-weak
940 global branch targets with default visibility can be preempted.
941 The resulting code is slightly bigger. This option only affects
942 the handling of branch instructions.
943 -mbig-obj
945 On x86-64 PE/COFF target this option forces the use of big object
946 file format, which allows more than 32768 sections.
947 -momit-lock-prefix=no
949 -momit-lock-prefix=yes
950 These options control how the assembler should encode lock prefix.
951 This option is intended as a workaround for processors, that fail
952 on lock prefix. This option can only be safely used with single-
953 core, single-thread computers -momit-lock-prefix=yes will omit all
954 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
955 usual, which is the default.
956 -mfence-as-lock-add=no
958 -mfence-as-lock-add=yes
959 These options control how the assembler should encode lfence,
960 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
961 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
962 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
963 encode lfence, mfence and sfence as usual, which is the default.
964 -mrelax-relocations=no
966 -mrelax-relocations=yes
967 These options control whether the assembler should generate relax
968 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
969 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
970 -mrelax-relocations=yes will generate relax relocations.
971 -mrelax-relocations=no will not generate relax relocations. The
972 default can be controlled by a configure option
973 --enable-x86-relax-relocations.
974 -mevexrcig=rne
976 -mevexrcig=rd
977 -mevexrcig=ru
978 -mevexrcig=rz
979 These options control how the assembler should encode SAE-only EVEX
980 instructions. -mevexrcig=rne will encode RC bits of EVEX
981 instruction with 00, which is the default. -mevexrcig=rd,
982 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
983 instructions with 01, 10 and 11 RC bits, respectively.
984 -mamd64
986 -mintel64
987 This option specifies that the assembler should accept only AMD64
988 or Intel64 ISA in 64-bit mode. The default is to accept both.
989 -O0 | -O | -O1 | -O2 | -Os
991 Optimize instruction encoding with smaller instruction size. -O
992 and -O1 encode 64-bit register load instructions with 64-bit
993 immediate as 32-bit register load instructions with 31-bit or
994 32-bits immediates and encode 64-bit register clearing instructions
995 with 32-bit register clearing instructions. -O2 includes -O1
996 optimization plus encodes 256-bit and 512-bit vector register
997 clearing instructions with 128-bit vector register clearing
998 instructions. -Os includes -O2 optimization plus encodes 16-bit,
999 32-bit and 64-bit register tests with immediate as 8-bit register
1000 test with immediate. -O0 turns off this optimization.
1001 The following options are available when as is configured for the
1003 Ubicom IP2K series.
1004 -mip2022ext
1006 Specifies that the extended IP2022 instructions are allowed.
1007 -mip2022
1009 Restores the default behaviour, which restricts the permitted
1010 instructions to just the basic IP2022 ones.
1011 The following options are available when as is configured for the
1013 Renesas M32C and M16C processors.
1014 -m32c
1016 Assemble M32C instructions.
1017 -m16c
1019 Assemble M16C instructions (the default).
1020 -relax
1022 Enable support for link-time relaxations.
1023 -h-tick-hex
1025 Support H'00 style hex constants in addition to 0x00 style.
1026 The following options are available when as is configured for the
1028 Renesas M32R (formerly Mitsubishi M32R) series.
1029 --m32rx
1031 Specify which processor in the M32R family is the target. The
1032 default is normally the M32R, but this option changes it to the
1033 M32RX.
1034 --warn-explicit-parallel-conflicts or --Wp
1036 Produce warning messages when questionable parallel constructs are
1037 encountered.
1038 --no-warn-explicit-parallel-conflicts or --Wnp
1040 Do not produce warning messages when questionable parallel
1041 constructs are encountered.
1042 The following options are available when as is configured for the
1044 Motorola 68000 series.
1045 -l Shorten references to undefined symbols, to one word instead of
1047 two.
1048 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1050 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1051 | -m68333 | -m68340 | -mcpu32 | -m5200
1052 Specify what processor in the 68000 family is the target. The
1053 default is normally the 68020, but this can be changed at
1054 configuration time.
1055 -m68881 | -m68882 | -mno-68881 | -mno-68882
1057 The target machine does (or does not) have a floating-point
1058 coprocessor. The default is to assume a coprocessor for 68020,
1059 68030, and cpu32. Although the basic 68000 is not compatible with
1060 the 68881, a combination of the two can be specified, since it's
1061 possible to do emulation of the coprocessor instructions with the
1062 main processor.
1063 -m68851 | -mno-68851
1065 The target machine does (or does not) have a memory-management unit
1066 coprocessor. The default is to assume an MMU for 68020 and up.
1067 The following options are available when as is configured for an Altera
1069 Nios II processor.
1070 -relax-section
1072 Replace identified out-of-range branches with PC-relative "jmp"
1073 sequences when possible. The generated code sequences are suitable
1074 for use in position-independent code, but there is a practical
1075 limit on the extended branch range because of the length of the
1076 sequences. This option is the default.
1077 -relax-all
1079 Replace branch instructions not determinable to be in range and all
1080 call instructions with "jmp" and "callr" sequences (respectively).
1081 This option generates absolute relocations against the target
1082 symbols and is not appropriate for position-independent code.
1083 -no-relax
1085 Do not replace any branches or calls.
1086 -EB Generate big-endian output.
1088 -EL Generate little-endian output. This is the default.
1090 -march=architecture
1092 This option specifies the target architecture. The assembler
1093 issues an error message if an attempt is made to assemble an
1094 instruction which will not execute on the target architecture. The
1095 following architecture names are recognized: "r1", "r2". The
1096 default is "r1".
1097 The following options are available when as is configured for a PRU
1099 processor.
1100 -mlink-relax
1102 Assume that LD would optimize LDI32 instructions by checking the
1103 upper 16 bits of the expression. If they are all zeros, then LD
1104 would shorten the LDI32 instruction to a single LDI. In such case
1105 "as" will output DIFF relocations for diff expressions.
1106 -mno-link-relax
1108 Assume that LD would not optimize LDI32 instructions. As a
1109 consequence, DIFF relocations will not be emitted.
1110 -mno-warn-regname-label
1112 Do not warn if a label name matches a register name. Usually
1113 assembler programmers will want this warning to be emitted. C
1114 compilers may want to turn this off.
1115 The following options are available when as is configured for a MIPS
1117 processor.
1118 -G num
1120 This option sets the largest size of an object that can be
1121 referenced implicitly with the "gp" register. It is only accepted
1122 for targets that use ECOFF format, such as a DECstation running
1123 Ultrix. The default value is 8.
1124 -EB Generate "big endian" format output.
1126 -EL Generate "little endian" format output.
1128 -mips1
1130 -mips2
1131 -mips3
1132 -mips4
1133 -mips5
1134 -mips32
1135 -mips32r2
1136 -mips32r3
1137 -mips32r5
1138 -mips32r6
1139 -mips64
1140 -mips64r2
1141 -mips64r3
1142 -mips64r5
1143 -mips64r6
1144 Generate code for a particular MIPS Instruction Set Architecture
1145 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1146 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1147 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1148 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1149 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1150 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1151 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1152 Release 6 ISA processors, respectively.
1153 -march=cpu
1155 Generate code for a particular MIPS CPU.
1156 -mtune=cpu
1158 Schedule and tune for a particular MIPS CPU.
1159 -mfix7000
1161 -mno-fix7000
1162 Cause nops to be inserted if the read of the destination register
1163 of an mfhi or mflo instruction occurs in the following two
1164 instructions.
1165 -mfix-rm7000
1167 -mno-fix-rm7000
1168 Cause nops to be inserted if a dmult or dmultu instruction is
1169 followed by a load instruction.
1170 -mdebug
1172 -no-mdebug
1173 Cause stabs-style debugging output to go into an ECOFF-style
1174 .mdebug section instead of the standard ELF .stabs sections.
1175 -mpdr
1177 -mno-pdr
1178 Control generation of ".pdr" sections.
1179 -mgp32
1181 -mfp32
1182 The register sizes are normally inferred from the ISA and ABI, but
1183 these flags force a certain group of registers to be treated as 32
1184 bits wide at all times. -mgp32 controls the size of general-
1185 purpose registers and -mfp32 controls the size of floating-point
1186 registers.
1187 -mgp64
1189 -mfp64
1190 The register sizes are normally inferred from the ISA and ABI, but
1191 these flags force a certain group of registers to be treated as 64
1192 bits wide at all times. -mgp64 controls the size of general-
1193 purpose registers and -mfp64 controls the size of floating-point
1194 registers.
1195 -mfpxx
1197 The register sizes are normally inferred from the ISA and ABI, but
1198 using this flag in combination with -mabi=32 enables an ABI variant
1199 which will operate correctly with floating-point registers which
1200 are 32 or 64 bits wide.
1201 -modd-spreg
1203 -mno-odd-spreg
1204 Enable use of floating-point operations on odd-numbered single-
1205 precision registers when supported by the ISA. -mfpxx implies
1206 -mno-odd-spreg, otherwise the default is -modd-spreg.
1207 -mips16
1209 -no-mips16
1210 Generate code for the MIPS 16 processor. This is equivalent to
1211 putting ".module mips16" at the start of the assembly file.
1212 -no-mips16 turns off this option.
1213 -mmips16e2
1215 -mno-mips16e2
1216 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1217 equivalent to putting ".module mips16e2" at the start of the
1218 assembly file. -mno-mips16e2 turns off this option.
1219 -mmicromips
1221 -mno-micromips
1222 Generate code for the microMIPS processor. This is equivalent to
1223 putting ".module micromips" at the start of the assembly file.
1224 -mno-micromips turns off this option. This is equivalent to
1225 putting ".module nomicromips" at the start of the assembly file.
1226 -msmartmips
1228 -mno-smartmips
1229 Enables the SmartMIPS extension to the MIPS32 instruction set.
1230 This is equivalent to putting ".module smartmips" at the start of
1231 the assembly file. -mno-smartmips turns off this option.
1232 -mips3d
1234 -no-mips3d
1235 Generate code for the MIPS-3D Application Specific Extension. This
1236 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1237 turns off this option.
1238 -mdmx
1240 -no-mdmx
1241 Generate code for the MDMX Application Specific Extension. This
1242 tells the assembler to accept MDMX instructions. -no-mdmx turns
1243 off this option.
1244 -mdsp
1246 -mno-dsp
1247 Generate code for the DSP Release 1 Application Specific Extension.
1248 This tells the assembler to accept DSP Release 1 instructions.
1249 -mno-dsp turns off this option.
1250 -mdspr2
1252 -mno-dspr2
1253 Generate code for the DSP Release 2 Application Specific Extension.
1254 This option implies -mdsp. This tells the assembler to accept DSP
1255 Release 2 instructions. -mno-dspr2 turns off this option.
1256 -mdspr3
1258 -mno-dspr3
1259 Generate code for the DSP Release 3 Application Specific Extension.
1260 This option implies -mdsp and -mdspr2. This tells the assembler to
1261 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1262 option.
1263 -mmsa
1265 -mno-msa
1266 Generate code for the MIPS SIMD Architecture Extension. This tells
1267 the assembler to accept MSA instructions. -mno-msa turns off this
1268 option.
1269 -mxpa
1271 -mno-xpa
1272 Generate code for the MIPS eXtended Physical Address (XPA)
1273 Extension. This tells the assembler to accept XPA instructions.
1274 -mno-xpa turns off this option.
1275 -mmt
1277 -mno-mt
1278 Generate code for the MT Application Specific Extension. This
1279 tells the assembler to accept MT instructions. -mno-mt turns off
1280 this option.
1281 -mmcu
1283 -mno-mcu
1284 Generate code for the MCU Application Specific Extension. This
1285 tells the assembler to accept MCU instructions. -mno-mcu turns off
1286 this option.
1287 -mcrc
1289 -mno-crc
1290 Generate code for the MIPS cyclic redundancy check (CRC)
1291 Application Specific Extension. This tells the assembler to accept
1292 CRC instructions. -mno-crc turns off this option.
1293 -mginv
1295 -mno-ginv
1296 Generate code for the Global INValidate (GINV) Application Specific
1297 Extension. This tells the assembler to accept GINV instructions.
1298 -mno-ginv turns off this option.
1299 -minsn32
1301 -mno-insn32
1302 Only use 32-bit instruction encodings when generating code for the
1303 microMIPS processor. This option inhibits the use of any 16-bit
1304 instructions. This is equivalent to putting ".set insn32" at the
1305 start of the assembly file. -mno-insn32 turns off this option.
1306 This is equivalent to putting ".set noinsn32" at the start of the
1307 assembly file. By default -mno-insn32 is selected, allowing all
1308 instructions to be used.
1309 --construct-floats
1311 --no-construct-floats
1312 The --no-construct-floats option disables the construction of
1313 double width floating point constants by loading the two halves of
1314 the value into the two single width floating point registers that
1315 make up the double width register. By default --construct-floats
1316 is selected, allowing construction of these floating point
1317 constants.
1318 --relax-branch
1320 --no-relax-branch
1321 The --relax-branch option enables the relaxation of out-of-range
1322 branches. By default --no-relax-branch is selected, causing any
1323 out-of-range branches to produce an error.
1324 -mignore-branch-isa
1326 -mno-ignore-branch-isa
1327 Ignore branch checks for invalid transitions between ISA modes.
1328 The semantics of branches does not provide for an ISA mode switch,
1329 so in most cases the ISA mode a branch has been encoded for has to
1330 be the same as the ISA mode of the branch's target label.
1331 Therefore GAS has checks implemented that verify in branch assembly
1332 that the two ISA modes match. -mignore-branch-isa disables these
1333 checks. By default -mno-ignore-branch-isa is selected, causing any
1334 invalid branch requiring a transition between ISA modes to produce
1335 an error.
1336 -mnan=encoding
1338 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1339 (-mnan=legacy) NaN encoding format. The latter is the default.
1340 --emulation=name
1342 This option was formerly used to switch between ELF and ECOFF
1343 output on targets like IRIX 5 that supported both. MIPS ECOFF
1344 support was removed in GAS 2.24, so the option now serves little
1345 purpose. It is retained for backwards compatibility.
1346 The available configuration names are: mipself, mipslelf and
1348 mipsbelf. Choosing mipself now has no effect, since the output is
1349 always ELF. mipslelf and mipsbelf select little- and big-endian
1350 output respectively, but -EL and -EB are now the preferred options
1351 instead.
1352 -nocpp
1354 as ignores this option. It is accepted for compatibility with the
1355 native tools.
1356 --trap
1358 --no-trap
1359 --break
1360 --no-break
1361 Control how to deal with multiplication overflow and division by
1362 zero. --trap or --no-break (which are synonyms) take a trap
1363 exception (and only work for Instruction Set Architecture level 2
1364 and higher); --break or --no-trap (also synonyms, and the default)
1365 take a break exception.
1366 -n When this option is used, as will issue a warning every time it
1368 generates a nop instruction from a macro.
1369 The following options are available when as is configured for a Meta
1371 processor.
1372 "-mcpu=metac11"
1374 Generate code for Meta 1.1.
1375 "-mcpu=metac12"
1377 Generate code for Meta 1.2.
1378 "-mcpu=metac21"
1380 Generate code for Meta 2.1.
1381 "-mfpu=metac21"
1383 Allow code to use FPU hardware of Meta 2.1.
1384 See the info pages for documentation of the MMIX-specific options.
1386 The following options are available when as is configured for a NDS32
1388 processor.
1389 "-O1"
1391 Optimize for performance.
1392 "-Os"
1394 Optimize for space.
1395 "-EL"
1397 Produce little endian data output.
1398 "-EB"
1400 Produce little endian data output.
1401 "-mpic"
1403 Generate PIC.
1404 "-mno-fp-as-gp-relax"
1406 Suppress fp-as-gp relaxation for this file.
1407 "-mb2bb-relax"
1409 Back-to-back branch optimization.
1410 "-mno-all-relax"
1412 Suppress all relaxation for this file.
1413 "-march=<arch name>"
1415 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1416 v3f, v3s, v2, v2j, v2f, v2s.
1417 "-mbaseline=<baseline>"
1419 Assemble for baseline <baseline> which could be v2, v3, v3m.
1420 "-mfpu-freg=FREG"
1422 Specify a FPU configuration.
1423 "0 8 SP / 4 DP registers"
1425 "1 16 SP / 8 DP registers"
1426 "2 32 SP / 16 DP registers"
1427 "3 32 SP / 32 DP registers"
1428 "-mabi=abi"
1429 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1430 "-m[no-]mac"
1432 Enable/Disable Multiply instructions support.
1433 "-m[no-]div"
1435 Enable/Disable Divide instructions support.
1436 "-m[no-]16bit-ext"
1438 Enable/Disable 16-bit extension
1439 "-m[no-]dx-regs"
1441 Enable/Disable d0/d1 registers
1442 "-m[no-]perf-ext"
1444 Enable/Disable Performance extension
1445 "-m[no-]perf2-ext"
1447 Enable/Disable Performance extension 2
1448 "-m[no-]string-ext"
1450 Enable/Disable String extension
1451 "-m[no-]reduced-regs"
1453 Enable/Disable Reduced Register configuration (GPR16) option
1454 "-m[no-]audio-isa-ext"
1456 Enable/Disable AUDIO ISA extension
1457 "-m[no-]fpu-sp-ext"
1459 Enable/Disable FPU SP extension
1460 "-m[no-]fpu-dp-ext"
1462 Enable/Disable FPU DP extension
1463 "-m[no-]fpu-fma"
1465 Enable/Disable FPU fused-multiply-add instructions
1466 "-mall-ext"
1468 Turn on all extensions and instructions support
1469 The following options are available when as is configured for a PowerPC
1471 processor.
1472 -a32
1474 Generate ELF32 or XCOFF32.
1475 -a64
1477 Generate ELF64 or XCOFF64.
1478 -K PIC
1480 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1481 -mpwrx | -mpwr2
1483 Generate code for POWER/2 (RIOS2).
1484 -mpwr
1486 Generate code for POWER (RIOS1)
1487 -m601
1489 Generate code for PowerPC 601.
1490 -mppc, -mppc32, -m603, -m604
1492 Generate code for PowerPC 603/604.
1493 -m403, -m405
1495 Generate code for PowerPC 403/405.
1496 -m440
1498 Generate code for PowerPC 440. BookE and some 405 instructions.
1499 -m464
1501 Generate code for PowerPC 464.
1502 -m476
1504 Generate code for PowerPC 476.
1505 -m7400, -m7410, -m7450, -m7455
1507 Generate code for PowerPC 7400/7410/7450/7455.
1508 -m750cl
1510 Generate code for PowerPC 750CL.
1511 -m821, -m850, -m860
1513 Generate code for PowerPC 821/850/860.
1514 -mppc64, -m620
1516 Generate code for PowerPC 620/625/630.
1517 -me500, -me500x2
1519 Generate code for Motorola e500 core complex.
1520 -me500mc
1522 Generate code for Freescale e500mc core complex.
1523 -me500mc64
1525 Generate code for Freescale e500mc64 core complex.
1526 -me5500
1528 Generate code for Freescale e5500 core complex.
1529 -me6500
1531 Generate code for Freescale e6500 core complex.
1532 -mspe
1534 Generate code for Motorola SPE instructions.
1535 -mspe2
1537 Generate code for Freescale SPE2 instructions.
1538 -mtitan
1540 Generate code for AppliedMicro Titan core complex.
1541 -mppc64bridge
1543 Generate code for PowerPC 64, including bridge insns.
1544 -mbooke
1546 Generate code for 32-bit BookE.
1547 -ma2
1549 Generate code for A2 architecture.
1550 -me300
1552 Generate code for PowerPC e300 family.
1553 -maltivec
1555 Generate code for processors with AltiVec instructions.
1556 -mvle
1558 Generate code for Freescale PowerPC VLE instructions.
1559 -mvsx
1561 Generate code for processors with Vector-Scalar (VSX) instructions.
1562 -mhtm
1564 Generate code for processors with Hardware Transactional Memory
1565 instructions.
1566 -mpower4, -mpwr4
1568 Generate code for Power4 architecture.
1569 -mpower5, -mpwr5, -mpwr5x
1571 Generate code for Power5 architecture.
1572 -mpower6, -mpwr6
1574 Generate code for Power6 architecture.
1575 -mpower7, -mpwr7
1577 Generate code for Power7 architecture.
1578 -mpower8, -mpwr8
1580 Generate code for Power8 architecture.
1581 -mpower9, -mpwr9
1583 Generate code for Power9 architecture.
1584 -mcell
1586 -mcell
1587 Generate code for Cell Broadband Engine architecture.
1588 -mcom
1590 Generate code Power/PowerPC common instructions.
1591 -many
1593 Generate code for any architecture (PWR/PWRX/PPC).
1594 -mregnames
1596 Allow symbolic names for registers.
1597 -mno-regnames
1599 Do not allow symbolic names for registers.
1600 -mrelocatable
1602 Support for GCC's -mrelocatable option.
1603 -mrelocatable-lib
1605 Support for GCC's -mrelocatable-lib option.
1606 -memb
1608 Set PPC_EMB bit in ELF flags.
1609 -mlittle, -mlittle-endian, -le
1611 Generate code for a little endian machine.
1612 -mbig, -mbig-endian, -be
1614 Generate code for a big endian machine.
1615 -msolaris
1617 Generate code for Solaris.
1618 -mno-solaris
1620 Do not generate code for Solaris.
1621 -nops=count
1623 If an alignment directive inserts more than count nops, put a
1624 branch at the beginning to skip execution of the nops.
1625 The following options are available when as is configured for a RISC-V
1627 processor.
1628 -fpic
1630 -fPIC
1631 Generate position-independent code
1632 -fno-pic
1634 Don't generate position-independent code (default)
1635 -march=ISA
1637 Select the base isa, as specified by ISA. For example
1638 -march=rv32ima.
1639 -mabi=ABI
1641 Selects the ABI, which is either "ilp32" or "lp64", optionally
1642 followed by "f", "d", or "q" to indicate single-precision, double-
1643 precision, or quad-precision floating-point calling convention, or
1644 none to indicate the soft-float calling convention. Also, "ilp32"
1645 can optionally be followed by "e" to indicate the RVE ABI, which is
1646 always soft-float.
1647 -mrelax
1649 Take advantage of linker relaxations to reduce the number of
1650 instructions required to materialize symbol addresses. (default)
1651 -mno-relax
1653 Don't do linker relaxations.
1654 See the info pages for documentation of the RX-specific options.
1656 The following options are available when as is configured for the s390
1658 processor family.
1659 -m31
1661 -m64
1662 Select the word size, either 31/32 bits or 64 bits.
1663 -mesa
1665 -mzarch
1666 Select the architecture mode, either the Enterprise System
1667 Architecture (esa) or the z/Architecture mode (zarch).
1668 -march=processor
1670 Specify which s390 processor variant is the target, g5 (or arch3),
1671 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
1672 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), or
1673 z14 (or arch12).
1674 -mregnames
1676 -mno-regnames
1677 Allow or disallow symbolic names for registers.
1678 -mwarn-areg-zero
1680 Warn whenever the operand for a base or index register has been
1681 specified but evaluates to zero.
1682 The following options are available when as is configured for a
1684 TMS320C6000 processor.
1685 -march=arch
1687 Enable (only) instructions from architecture arch. By default, all
1688 instructions are permitted.
1689 The following values of arch are accepted: "c62x", "c64x", "c64x+",
1691 "c67x", "c67x+", "c674x".
1692 -mdsbt
1694 -mno-dsbt
1695 The -mdsbt option causes the assembler to generate the
1696 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1697 code is using DSBT addressing. The -mno-dsbt option, the default,
1698 causes the tag to have a value of 0, indicating that the code does
1699 not use DSBT addressing. The linker will emit a warning if objects
1700 of different type (DSBT and non-DSBT) are linked together.
1701 -mpid=no
1703 -mpid=near
1704 -mpid=far
1705 The -mpid= option causes the assembler to generate the
1706 "Tag_ABI_PID" attribute with a value indicating the form of data
1707 addressing used by the code. -mpid=no, the default, indicates
1708 position-dependent data addressing, -mpid=near indicates position-
1709 independent addressing with GOT accesses using near DP addressing,
1710 and -mpid=far indicates position-independent addressing with GOT
1711 accesses using far DP addressing. The linker will emit a warning
1712 if objects built with different settings of this option are linked
1713 together.
1714 -mpic
1716 -mno-pic
1717 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1718 attribute with a value of 1, indicating that the code is using
1719 position-independent code addressing, The "-mno-pic" option, the
1720 default, causes the tag to have a value of 0, indicating position-
1721 dependent code addressing. The linker will emit a warning if
1722 objects of different type (position-dependent and position-
1723 independent) are linked together.
1724 -mbig-endian
1726 -mlittle-endian
1727 Generate code for the specified endianness. The default is little-
1728 endian.
1729 The following options are available when as is configured for a TILE-Gx
1731 processor.
1732 -m32 | -m64
1734 Select the word size, either 32 bits or 64 bits.
1735 -EB | -EL
1737 Select the endianness, either big-endian (-EB) or little-endian
1738 (-EL).
1739 The following option is available when as is configured for a Visium
1741 processor.
1742 -mtune=arch
1744 This option specifies the target architecture. If an attempt is
1745 made to assemble an instruction that will not execute on the target
1746 architecture, the assembler will issue an error message.
1747 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1749 The following options are available when as is configured for an Xtensa
1751 processor.
1752 --text-section-literals | --no-text-section-literals
1754 Control the treatment of literal pools. The default is
1755 --no-text-section-literals, which places literals in separate
1756 sections in the output file. This allows the literal pool to be
1757 placed in a data RAM/ROM. With --text-section-literals, the
1758 literals are interspersed in the text section in order to keep them
1759 as close as possible to their references. This may be necessary
1760 for large assembly files, where the literals would otherwise be out
1761 of range of the "L32R" instructions in the text section. Literals
1762 are grouped into pools following ".literal_position" directives or
1763 preceding "ENTRY" instructions. These options only affect literals
1764 referenced via PC-relative "L32R" instructions; literals for
1765 absolute mode "L32R" instructions are handled separately.
1766 --auto-litpools | --no-auto-litpools
1768 Control the treatment of literal pools. The default is
1769 --no-auto-litpools, which in the absence of --text-section-literals
1770 places literals in separate sections in the output file. This
1771 allows the literal pool to be placed in a data RAM/ROM. With
1772 --auto-litpools, the literals are interspersed in the text section
1773 in order to keep them as close as possible to their references,
1774 explicit ".literal_position" directives are not required. This may
1775 be necessary for very large functions, where single literal pool at
1776 the beginning of the function may not be reachable by "L32R"
1777 instructions at the end. These options only affect literals
1778 referenced via PC-relative "L32R" instructions; literals for
1779 absolute mode "L32R" instructions are handled separately. When
1780 used together with --text-section-literals, --auto-litpools takes
1781 precedence.
1782 --absolute-literals | --no-absolute-literals
1784 Indicate to the assembler whether "L32R" instructions use absolute
1785 or PC-relative addressing. If the processor includes the absolute
1786 addressing option, the default is to use absolute "L32R"
1787 relocations. Otherwise, only the PC-relative "L32R" relocations
1788 can be used.
1789 --target-align | --no-target-align
1791 Enable or disable automatic alignment to reduce branch penalties at
1792 some expense in code size. This optimization is enabled by
1793 default. Note that the assembler will always align instructions
1794 like "LOOP" that have fixed alignment requirements.
1795 --longcalls | --no-longcalls
1797 Enable or disable transformation of call instructions to allow
1798 calls across a greater range of addresses. This option should be
1799 used when call targets can potentially be out of range. It may
1800 degrade both code size and performance, but the linker can
1801 generally optimize away the unnecessary overhead when a call ends
1802 up within range. The default is --no-longcalls.
1803 --transform | --no-transform
1805 Enable or disable all assembler transformations of Xtensa
1806 instructions, including both relaxation and optimization. The
1807 default is --transform; --no-transform should only be used in the
1808 rare cases when the instructions must be exactly as specified in
1809 the assembly source. Using --no-transform causes out of range
1810 instruction operands to be errors.
1811 --rename-section oldname=newname
1813 Rename the oldname section to newname. This option can be used
1814 multiple times to rename multiple sections.
1815 --trampolines | --no-trampolines
1817 Enable or disable transformation of jump instructions to allow
1818 jumps across a greater range of addresses. This option should be
1819 used when jump targets can potentially be out of range. In the
1820 absence of such jumps this option does not affect code size or
1821 performance. The default is --trampolines.
1822 The following options are available when as is configured for a Z80
1824 family processor.
1825 -z80
1827 Assemble for Z80 processor.
1828 -r800
1830 Assemble for R800 processor.
1831 -ignore-undocumented-instructions
1833 -Wnud
1834 Assemble undocumented Z80 instructions that also work on R800
1835 without warning.
1836 -ignore-unportable-instructions
1838 -Wnup
1839 Assemble all undocumented Z80 instructions without warning.
1840 -warn-undocumented-instructions
1842 -Wud
1843 Issue a warning for undocumented Z80 instructions that also work on
1844 R800.
1845 -warn-unportable-instructions
1847 -Wup
1848 Issue a warning for undocumented Z80 instructions that do not work
1849 on R800.
1850 -forbid-undocumented-instructions
1852 -Fud
1853 Treat all undocumented instructions as errors.
1854 -forbid-unportable-instructions
1856 -Fup
1857 Treat undocumented Z80 instructions that do not work on R800 as
1858 errors.
1859
1861 gcc(1), ld(1), and the Info entries for binutils and ld.
1862
1864 Copyright (c) 1991-2018 Free Software Foundation, Inc.
1865 Permission is granted to copy, distribute and/or modify this document
1867 under the terms of the GNU Free Documentation License, Version 1.3 or
1868 any later version published by the Free Software Foundation; with no
1869 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1870 Texts. A copy of the license is included in the section entitled "GNU
1871 Free Documentation License".
1872binutils-2.31.1 2019-05-27 AS(1)