1GBZ80(7) BSD Miscellaneous Information Manual GBZ80(7)
2
4 gbz80 — CPU opcode reference
5
7 This is the list of opcodes supported by rgbasm(1), including a short
8 description, the number of bytes needed to encode them and the number of
9 CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10 them.
11 Note: All arithmetic/logic operations that use register A as destination
13 can omit the destination as it is assumed to be register A by default.
14 The following two lines have the same effect:
15 OR A,B
17 OR B
18
20 List of abbreviations used in this document.
21 r8 Any of the 8-bit registers (A, B, C, D, E, H, L).
23 r16 Any of the general-purpose 16-bit registers (BC, DE, HL).
25 n8 8-bit integer constant.
27 n16 16-bit integer constant.
29 e8 8-bit offset (-128 to 127).
31 u3 3-bit unsigned integer constant (0 to 7).
33 cc Condition codes:
35 Z Execute if Z is set.
36 NZ Execute if Z is not set.
37 C Execute if C is set.
38 NC Execute if C is not set.
39 vec One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28,
41 0x30 and 0x38).
42
44 8-bit Arithmetic and Logic Instructions
45 ADC A,r8
46 ADC A,[HL]
47 ADC A,n8
48 ADD A,r8
49 ADD A,[HL]
50 ADD A,n8
51 AND A,r8
52 AND A,[HL]
53 AND A,n8
54 CP A,r8
55 CP A,[HL]
56 CP A,n8
57 DEC r8
58 DEC [HL]
59 INC r8
60 INC [HL]
61 OR A,r8
62 OR A,[HL]
63 OR A,n8
64 SBC A,r8
65 SBC A,[HL]
66 SBC A,n8
67 SUB A,r8
68 SUB A,[HL]
69 SUB A,n8
70 XOR A,r8
71 XOR A,[HL]
72 XOR A,n8
73 16-bit Arithmetic Instructions
75 ADD HL,r16
76 DEC r16
77 INC r16
78 Bit Operations Instructions
80 BIT u3,r8
81 BIT u3,[HL]
82 RES u3,r8
83 RES u3,[HL]
84 SET u3,r8
85 SET u3,[HL]
86 SWAP r8
87 SWAP [HL]
88 Bit Shift Instructions
90 RL r8
91 RL [HL]
92 RLA
93 RLC r8
94 RLC [HL]
95 RLCA
96 RR r8
97 RR [HL]
98 RRA
99 RRC r8
100 RRC [HL]
101 RRCA
102 SLA r8
103 SLA [HL]
104 SRA r8
105 SRA [HL]
106 SRL r8
107 SRL [HL]
108 Load Instructions
110 LD r8,r8
111 LD r8,n8
112 LD r16,n16
113 LD [HL],r8
114 LD [HL],n8
115 LD r8,[HL]
116 LD [r16],A
117 LD [n16],A
118 LDH [n16],A
119 LDH [C],A
120 LD A,[r16]
121 LD A,[n16]
122 LDH A,[n16]
123 LDH A,[C]
124 LD [HLI],A
125 LD [HLD],A
126 LD A,[HLI]
127 LD A,[HLD]
128 Jumps and Subroutines
130 CALL n16
131 CALL cc,n16
132 JP HL
133 JP n16
134 JP cc,n16
135 JR e8
136 JR cc,e8
137 RET cc
138 RET
139 RETI
140 RST vec
141 Stack Operations Instructions
143 ADD HL,SP
144 ADD SP,e8
145 DEC SP
146 INC SP
147 LD SP,n16
148 LD [n16],SP
149 LD HL,SP+e8
150 LD SP,HL
151 POP AF
152 POP r16
153 PUSH AF
154 PUSH r16
155 Miscellaneous Instructions
157 CCF
158 CPL
159 DAA
160 DI
161 EI
162 HALT
163 NOP
164 SCF
165 STOP
166
168 ADC A,r8
169 Add the value in r8 plus the carry flag to A.
170 Cycles: 1
172 Bytes: 1
174 Flags:
176 Z Set if result is 0.
177 N 0
178 H Set if overflow from bit 3.
179 C Set if overflow from bit 7.
180 ADC A,[HL]
182 Add the byte pointed to by HL plus the carry flag to A.
183 Cycles: 2
185 Bytes: 1
187 Flags: See ADC A,r8
189 ADC A,n8
191 Add the value n8 plus the carry flag to A.
192 Cycles: 2
194 Bytes: 2
196 Flags: See ADC A,r8
198 ADD A,r8
200 Add the value in r8 to A.
201 Cycles: 1
203 Bytes: 1
205 Flags:
207 Z Set if result is 0.
208 N 0
209 H Set if overflow from bit 3.
210 C Set if overflow from bit 7.
211 ADD A,[HL]
213 Add the byte pointed to by HL to A.
214 Cycles: 2
216 Bytes: 1
218 Flags: See ADD A,r8
220 ADD A,n8
222 Add the value n8 to A.
223 Cycles: 2
225 Bytes: 2
227 Flags: See ADD A,r8
229 ADD HL,r16
231 Add the value in r16 to HL.
232 Cycles: 2
234 Bytes: 1
236 Flags:
238 N 0
239 H Set if overflow from bit 11.
240 C Set if overflow from bit 15.
241 ADD HL,SP
243 Add the value in SP to HL.
244 Cycles: 2
246 Bytes: 1
248 Flags: See ADD HL,r16
250 ADD SP,e8
252 Add the signed value e8 to SP.
253 Cycles: 4
255 Bytes: 2
257 Flags:
259 Z 0
260 N 0
261 H Set if overflow from bit 3.
262 C Set if overflow from bit 7.
263 AND A,r8
265 Bitwise AND between the value in r8 and A.
266 Cycles: 1
268 Bytes: 1
270 Flags:
272 Z Set if result is 0.
273 N 0
274 H 1
275 C 0
276 AND A,[HL]
278 Bitwise AND between the byte pointed to by HL and A.
279 Cycles: 2
281 Bytes: 1
283 Flags: See AND A,r8
285 AND A,n8
287 Bitwise AND between the value in n8 and A.
288 Cycles: 2
290 Bytes: 2
292 Flags: See AND A,r8
294 BIT u3,r8
296 Test bit u3 in register r8, set the zero flag if bit not set.
297 Cycles: 2
299 Bytes: 2
301 Flags:
303 Z Set if the selected bit is 0.
304 N 0
305 H 1
306 BIT u3,[HL]
308 Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
309 Cycles: 3
311 Bytes: 2
313 Flags: See BIT u3,r8
315 CALL n16
317 Call address n16. This pushes the address of the instruction after the
318 CALL on the stack, such that RET can pop it later; then, it executes an
319 implicit JP n16.
320 Cycles: 6
322 Bytes: 3
324 Flags: None affected.
326 CALL cc,n16
328 Call address n16 if condition cc is met.
329 Cycles: 6 taken / 3 untaken
331 Bytes: 3
333 Flags: None affected.
335 CCF
337 Complement Carry Flag.
338 Cycles: 1
340 Bytes: 1
342 Flags:
344 N 0
345 H 0
346 C Inverted.
347 CP A,r8
349 Subtract the value in r8 from A and set flags accordingly, but don't
350 store the result. This is useful for ComParing values.
351 Cycles: 1
353 Bytes: 1
355 Flags:
357 Z Set if result is 0.
358 N 1
359 H Set if borrow from bit 4.
360 C Set if borrow (i.e. if r8 > A).
361 CP A,[HL]
363 Subtract the byte pointed to by HL from A and set flags accordingly, but
364 don't store the result.
365 Cycles: 2
367 Bytes: 1
369 Flags: See CP A,r8
371 CP A,n8
373 Subtract the value n8 from A and set flags accordingly, but don't store
374 the result.
375 Cycles: 2
377 Bytes: 2
379 Flags: See CP A,r8
381 CPL
383 ComPLement accumulator (A = ~A).
384 Cycles: 1
386 Bytes: 1
388 Flags:
390 N 1
391 H 1
392 DAA
394 Decimal Adjust Accumulator to get a correct BCD representation after an
395 arithmetic instruction.
396 Cycles: 1
398 Bytes: 1
400 Flags:
402 Z Set if result is 0.
403 H 0
404 C Set or reset depending on the operation.
405 DEC r8
407 Decrement value in register r8 by 1.
408 Cycles: 1
410 Bytes: 1
412 Flags:
414 Z Set if result is 0.
415 N 1
416 H Set if borrow from bit 4.
417 DEC [HL]
419 Decrement the byte pointed to by HL by 1.
420 Cycles: 3
422 Bytes: 1
424 Flags: See DEC r8
426 DEC r16
428 Decrement value in register r16 by 1.
429 Cycles: 2
431 Bytes: 1
433 Flags: None affected.
435 DEC SP
437 Decrement value in register SP by 1.
438 Cycles: 2
440 Bytes: 1
442 Flags: None affected.
444 DI
446 Disable Interrupts by clearing the IME flag.
447 Cycles: 1
449 Bytes: 1
451 Flags: None affected.
453 EI
455 Enable Interrupts by setting the IME flag. The flag is only set after
456 the instruction following EI.
457 Cycles: 1
459 Bytes: 1
461 Flags: None affected.
463 HALT
465 Enter CPU low-power consumption mode until an interrupt occurs. The
466 exact behavior of this instruction depends on the state of the IME flag.
467 IME set
469 The CPU enters low-power mode until after an interrupt is about
470 to be serviced. The handler is executed normally, and the CPU
471 resumes execution after the HALT when that returns.
472 IME not set
474 The behavior depends on whether an interrupt is pending (i.e.
475 ‘[IE] & [IF]’ is non-zero).
476 None pending
478 As soon as an interrupt becomes pending, the CPU resumes
479 execution. This is like the above, except that the han‐
480 dler is not called.
481 Some pending
483 The CPU continues execution after the HALT, but the byte
484 after it is read twice in a row (PC is not incremented,
485 due to a hardware bug).
486 Cycles: -
488 Bytes: 1
490 Flags: None affected.
492 INC r8
494 Increment value in register r8 by 1.
495 Cycles: 1
497 Bytes: 1
499 Flags:
501 Z Set if result is 0.
502 N 0
503 H Set if overflow from bit 3.
504 INC [HL]
506 Increment the byte pointed to by HL by 1.
507 Cycles: 3
509 Bytes: 1
511 Flags: See INC r8
513 INC r16
515 Increment value in register r16 by 1.
516 Cycles: 2
518 Bytes: 1
520 Flags: None affected.
522 INC SP
524 Increment value in register SP by 1.
525 Cycles: 2
527 Bytes: 1
529 Flags: None affected.
531 JP n16
533 Jump to address n16; effectively, store n16 into PC.
534 Cycles: 4
536 Bytes: 3
538 Flags: None affected.
540 JP cc,n16
542 Jump to address n16 if condition cc is met.
543 Cycles: 4 taken / 3 untaken
545 Bytes: 3
547 Flags: None affected.
549 JP HL
551 Jump to address in HL; effectively, load PC with value in register HL.
552 Cycles: 1
554 Bytes: 1
556 Flags: None affected.
558 JR e8
560 Relative Jump by adding e8 to the address of the instruction following
561 the JR. To clarify, an operand of 0 is equivalent to no jumping.
562 Cycles: 3
564 Bytes: 2
566 Flags: None affected.
568 JR cc,e8
570 Relative Jump by adding e8 to the current address if condition cc is met.
571 Cycles: 3 taken / 2 untaken
573 Bytes: 2
575 Flags: None affected.
577 LD r8,r8
579 Load (copy) value in register on the right into register on the left.
580 Cycles: 1
582 Bytes: 1
584 Flags: None affected.
586 LD r8,n8
588 Load value n8 into register r8.
589 Cycles: 2
591 Bytes: 2
593 Flags: None affected.
595 LD r16,n16
597 Load value n16 into register r16.
598 Cycles: 3
600 Bytes: 3
602 Flags: None affected.
604 LD [HL],r8
606 Store value in register r8 into byte pointed to by register HL.
607 Cycles: 2
609 Bytes: 1
611 Flags: None affected.
613 LD [HL],n8
615 Store value n8 into byte pointed to by register HL.
616 Cycles: 3
618 Bytes: 2
620 Flags: None affected.
622 LD r8,[HL]
624 Load value into register r8 from byte pointed to by register HL.
625 Cycles: 2
627 Bytes: 1
629 Flags: None affected.
631 LD [r16],A
633 Store value in register A into byte pointed to by register r16.
634 Cycles: 2
636 Bytes: 1
638 Flags: None affected.
640 LD [n16],A
642 Store value in register A into byte at address n16.
643 Cycles: 4
645 Bytes: 3
647 Flags: None affected.
649 LDH [n16],A
651 Store value in register A into byte at address n16, provided it is
652 between $FF00 and $FFFF.
653 Cycles: 3
655 Bytes: 2
657 Flags: None affected.
659 This is sometimes written as ‘ldio [n16], a’, or ‘ld [$ff00+n8], a’.
661 LDH [C],A
663 Store value in register A into byte at address $FF00+C.
664 Cycles: 2
666 Bytes: 1
668 Flags: None affected.
670 This is sometimes written as ‘ldio [c], a’, or ‘ld [$ff00+c], a’.
672 LD A,[r16]
674 Load value in register A from byte pointed to by register r16.
675 Cycles: 2
677 Bytes: 1
679 Flags: None affected.
681 LD A,[n16]
683 Load value in register A from byte at address n16.
684 Cycles: 4
686 Bytes: 3
688 Flags: None affected.
690 LDH A,[n16]
692 Load value in register A from byte at address n16, provided it is between
693 $FF00 and $FFFF.
694 Cycles: 3
696 Bytes: 2
698 Flags: None affected.
700 This is sometimes written as ‘ldio a, [n16]’, or ‘ld a, [$ff00+n8]’.
702 LDH A,[C]
704 Load value in register A from byte at address $FF00+c.
705 Cycles: 2
707 Bytes: 1
709 Flags: None affected.
711 This is sometimes written as ‘ldio a, [c]’, or ‘ld a, [$ff00+c]’.
713 LD [HLI],A
715 Store value in register A into byte pointed by HL and increment HL after‐
716 wards.
717 Cycles: 2
719 Bytes: 1
721 Flags: None affected.
723 LD [HLD],A
725 Store value in register A into byte pointed by HL and decrement HL after‐
726 wards.
727 Cycles: 2
729 Bytes: 1
731 Flags: None affected.
733 LD A,[HLD]
735 Load value into register A from byte pointed by HL and decrement HL
736 afterwards.
737 Cycles: 2
739 Bytes: 1
741 Flags: None affected.
743 LD A,[HLI]
745 Load value into register A from byte pointed by HL and increment HL
746 afterwards.
747 Cycles: 2
749 Bytes: 1
751 Flags: None affected.
753 LD SP,n16
755 Load value n16 into register SP.
756 Cycles: 3
758 Bytes: 3
760 Flags: None affected.
762 LD [n16],SP
764 Store SP & $FF at address n16 and SP >> 8 at address n16 + 1.
765 Cycles: 5
767 Bytes: 3
769 Flags: None affected.
771 LD HL,SP+e8
773 Add the signed value e8 to SP and store the result in HL.
774 Cycles: 3
776 Bytes: 2
778 Flags:
780 Z 0
781 N 0
782 H Set if overflow from bit 3.
783 C Set if overflow from bit 7.
784 LD SP,HL
786 Load register HL into register SP.
787 Cycles: 2
789 Bytes: 1
791 Flags: None affected.
793 NOP
795 No OPeration.
796 Cycles: 1
798 Bytes: 1
800 Flags: None affected.
802 OR A,r8
804 Store into A the bitwise OR of the value in r8 and A.
805 Cycles: 1
807 Bytes: 1
809 Flags:
811 Z Set if result is 0.
812 N 0
813 H 0
814 C 0
815 OR A,[HL]
817 Store into A the bitwise OR of the byte pointed to by HL and A.
818 Cycles: 2
820 Bytes: 1
822 Flags: See OR A,r8
824 OR A,n8
826 Store into A the bitwise OR of n8 and A.
827 Cycles: 2
829 Bytes: 2
831 Flags: See OR A,r8
833 POP AF
835 Pop register AF from the stack. This is roughly equivalent to the fol‐
836 lowing imaginary instructions:
837 ld f, [sp] ; See below for individual flags
839 inc sp
840 ld a, [sp]
841 inc sp
842 Cycles: 3
844 Bytes: 1
846 Flags:
848 Z Set from bit 7 of the popped low byte.
849 N Set from bit 6 of the popped low byte.
850 H Set from bit 5 of the popped low byte.
851 C Set from bit 4 of the popped low byte.
852 POP r16
854 Pop register r16 from the stack. This is roughly equivalent to the fol‐
855 lowing imaginary instructions:
856 ld LOW(r16), [sp] ; C, E or L
858 inc sp
859 ld HIGH(r16), [sp] ; B, D or H
860 inc sp
861 Cycles: 3
863 Bytes: 1
865 Flags: None affected.
867 PUSH AF
869 Push register AF into the stack. This is roughly equivalent to the fol‐
870 lowing imaginary instructions:
871 dec sp
873 ld [sp], a
874 dec sp
875 ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4
876 Cycles: 4
878 Bytes: 1
880 Flags: None affected.
882 PUSH r16
884 Push register r16 into the stack. This is roughly equivalent to the fol‐
885 lowing imaginary instructions:
886 dec sp
888 ld [sp], HIGH(r16) ; B, D or H
889 dec sp
890 ld [sp], LOW(r16) ; C, E or L
891 Cycles: 4
893 Bytes: 1
895 Flags: None affected.
897 RES u3,r8
899 Set bit u3 in register r8 to 0. Bit 0 is the rightmost one, bit 7 the
900 leftmost one.
901 Cycles: 2
903 Bytes: 2
905 Flags: None affected.
907 RES u3,[HL]
909 Set bit u3 in the byte pointed by HL to 0. Bit 0 is the rightmost one,
910 bit 7 the leftmost one.
911 Cycles: 4
913 Bytes: 2
915 Flags: None affected.
917 RET
919 Return from subroutine. This is basically a POP PC (if such an instruc‐
920 tion existed). See POP r16 for an explanation of how POP works.
921 Cycles: 4
923 Bytes: 1
925 Flags: None affected.
927 RET cc
929 Return from subroutine if condition cc is met.
930 Cycles: 5 taken / 2 untaken
932 Bytes: 1
934 Flags: None affected.
936 RETI
938 Return from subroutine and enable interrupts. This is basically equiva‐
939 lent to executing EI then RET, meaning that IME is set right after this
940 instruction.
941 Cycles: 4
943 Bytes: 1
945 Flags: None affected.
947 RL r8
949 Rotate bits in register r8 left through carry.
950 C <- [7 <- 0] <- C
952 Cycles: 2
954 Bytes: 2
956 Flags:
958 Z Set if result is 0.
959 N 0
960 H 0
961 C Set according to result.
962 RL [HL]
964 Rotate byte pointed to by HL left through carry.
965 C <- [7 <- 0] <- C
967 Cycles: 4
969 Bytes: 2
971 Flags: See RL r8
973 RLA
975 Rotate register A left through carry.
976 C <- [7 <- 0] <- C
978 Cycles: 1
980 Bytes: 1
982 Flags:
984 Z 0
985 N 0
986 H 0
987 C Set according to result.
988 RLC r8
990 Rotate register r8 left.
991 C <- [7 <- 0] <- [7]
993 Cycles: 2
995 Bytes: 2
997 Flags:
999 Z Set if result is 0.
1000 N 0
1001 H 0
1002 C Set according to result.
1003 RLC [HL]
1005 Rotate byte pointed to by HL left.
1006 C <- [7 <- 0] <- [7]
1008 Cycles: 4
1010 Bytes: 2
1012 Flags: See RLC r8
1014 RLCA
1016 Rotate register A left.
1017 C <- [7 <- 0] <- [7]
1019 Cycles: 1
1021 Bytes: 1
1023 Flags:
1025 Z 0
1026 N 0
1027 H 0
1028 C Set according to result.
1029 RR r8
1031 Rotate register r8 right through carry.
1032 C -> [7 -> 0] -> C
1034 Cycles: 2
1036 Bytes: 2
1038 Flags:
1040 Z Set if result is 0.
1041 N 0
1042 H 0
1043 C Set according to result.
1044 RR [HL]
1046 Rotate byte pointed to by HL right through carry.
1047 C -> [7 -> 0] -> C
1049 Cycles: 4
1051 Bytes: 2
1053 Flags: See RR r8
1055 RRA
1057 Rotate register A right through carry.
1058 C -> [7 -> 0] -> C
1060 Cycles: 1
1062 Bytes: 1
1064 Flags:
1066 Z 0
1067 N 0
1068 H 0
1069 C Set according to result.
1070 RRC r8
1072 Rotate register r8 right.
1073 [0] -> [7 -> 0] -> C
1075 Cycles: 2
1077 Bytes: 2
1079 Flags:
1081 Z Set if result is 0.
1082 N 0
1083 H 0
1084 C Set according to result.
1085 RRC [HL]
1087 Rotate byte pointed to by HL right.
1088 [0] -> [7 -> 0] -> C
1090 Cycles: 4
1092 Bytes: 2
1094 Flags: See RRC r8
1096 RRCA
1098 Rotate register A right.
1099 [0] -> [7 -> 0] -> C
1101 Cycles: 1
1103 Bytes: 1
1105 Flags:
1107 Z 0
1108 N 0
1109 H 0
1110 C Set according to result.
1111 RST vec
1113 Call address vec. This is a shorter and faster equivalent to CALL for
1114 suitable values of vec.
1115 Cycles: 4
1117 Bytes: 1
1119 Flags: None affected.
1121 SBC A,r8
1123 Subtract the value in r8 and the carry flag from A.
1124 Cycles: 1
1126 Bytes: 1
1128 Flags:
1130 Z Set if result is 0.
1131 N 1
1132 H Set if borrow from bit 4.
1133 C Set if borrow (i.e. if (r8 + carry) > A).
1134 SBC A,[HL]
1136 Subtract the byte pointed to by HL and the carry flag from A.
1137 Cycles: 2
1139 Bytes: 1
1141 Flags: See SBC A,r8
1143 SBC A,n8
1145 Subtract the value n8 and the carry flag from A.
1146 Cycles: 2
1148 Bytes: 2
1150 Flags: See SBC A,r8
1152 SCF
1154 Set Carry Flag.
1155 Cycles: 1
1157 Bytes: 1
1159 Flags:
1161 N 0
1162 H 0
1163 C 1
1164 SET u3,r8
1166 Set bit u3 in register r8 to 1. Bit 0 is the rightmost one, bit 7 the
1167 leftmost one.
1168 Cycles: 2
1170 Bytes: 2
1172 Flags: None affected.
1174 SET u3,[HL]
1176 Set bit u3 in the byte pointed by HL to 1. Bit 0 is the rightmost one,
1177 bit 7 the leftmost one.
1178 Cycles: 4
1180 Bytes: 2
1182 Flags: None affected.
1184 SLA r8
1186 Shift Left Arithmetic register r8.
1187 C <- [7 <- 0] <- 0
1189 Cycles: 2
1191 Bytes: 2
1193 Flags:
1195 Z Set if result is 0.
1196 N 0
1197 H 0
1198 C Set according to result.
1199 SLA [HL]
1201 Shift Left Arithmetic byte pointed to by HL.
1202 C <- [7 <- 0] <- 0
1204 Cycles: 4
1206 Bytes: 2
1208 Flags: See SLA r8
1210 SRA r8
1212 Shift Right Arithmetic register r8.
1213 [7] -> [7 -> 0] -> C
1215 Cycles: 2
1217 Bytes: 2
1219 Flags:
1221 Z Set if result is 0.
1222 N 0
1223 H 0
1224 C Set according to result.
1225 SRA [HL]
1227 Shift Right Arithmetic byte pointed to by HL.
1228 [7] -> [7 -> 0] -> C
1230 Cycles: 4
1232 Bytes: 2
1234 Flags: See SRA r8
1236 SRL r8
1238 Shift Right Logic register r8.
1239 0 -> [7 -> 0] -> C
1241 Cycles: 2
1243 Bytes: 2
1245 Flags:
1247 Z Set if result is 0.
1248 N 0
1249 H 0
1250 C Set according to result.
1251 SRL [HL]
1253 Shift Right Logic byte pointed to by HL.
1254 0 -> [7 -> 0] -> C
1256 Cycles: 4
1258 Bytes: 2
1260 Flags: See SRA r8
1262 STOP
1264 Enter CPU very low power mode. Also used to switch between double and
1265 normal speed CPU modes in GBC.
1266 Cycles: -
1268 Bytes: 2
1270 Flags: None affected.
1272 SUB A,r8
1274 Subtract the value in r8 from A.
1275 Cycles: 1
1277 Bytes: 1
1279 Flags:
1281 Z Set if result is 0.
1282 N 1
1283 H Set if borrow from bit 4.
1284 C Set if borrow (set if r8 > A).
1285 SUB A,[HL]
1287 Subtract the byte pointed to by HL from A.
1288 Cycles: 2
1290 Bytes: 1
1292 Flags: See SUB A,r8
1294 SUB A,n8
1296 Subtract the value n8 from A.
1297 Cycles: 2
1299 Bytes: 2
1301 Flags: See SUB A,r8
1303 SWAP r8
1305 Swap upper 4 bits in register r8 and the lower 4 ones.
1306 Cycles: 2
1308 Bytes: 2
1310 Flags:
1312 Z Set if result is 0.
1313 N 0
1314 H 0
1315 C 0
1316 SWAP [HL]
1318 Swap upper 4 bits in the byte pointed by HL and the lower 4 ones.
1319 Cycles: 4
1321 Bytes: 2
1323 Flags: See SWAP r8
1325 XOR A,r8
1327 Bitwise XOR between the value in r8 and A.
1328 Cycles: 1
1330 Bytes: 1
1332 Flags:
1334 Z Set if result is 0.
1335 N 0
1336 H 0
1337 C 0
1338 XOR A,[HL]
1340 Bitwise XOR between the byte pointed to by HL and A.
1341 Cycles: 2
1343 Bytes: 1
1345 Flags: See XOR A,r8
1347 XOR A,n8
1349 Bitwise XOR between the value in n8 and A.
1350 Cycles: 2
1352 Bytes: 2
1354 Flags: See XOR A,r8
1356
1358 rgbasm(1), rgbds(7)
1359
1361 rgbds was originally written by Carsten Sørensen as part of the ASMotor
1362 package, and was later packaged in RGBDS by Justin Lloyd. It is now
1363 maintained by a number of contributors at .:
1364 https://github.com/gbdev/rgbds
1365BSD February 23, 2018 BSD