1GBZ80(7) BSD Miscellaneous Information Manual GBZ80(7)
2
4 gbz80 — CPU opcode reference
5
7 This is the list of opcodes supported by rgbasm(1), including a short de‐
8 scription, the number of bytes needed to encode them and the number of
9 CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10 them.
11 Note: All arithmetic/logic operations that use register A as destination
13 can omit the destination as it is assumed to be register A by default.
14 The following two lines have the same effect:
15 OR A,B
17 OR B
18
20 List of abbreviations used in this document.
21 r8 Any of the 8-bit registers (A, B, C, D, E, H, L).
23 r16 Any of the general-purpose 16-bit registers (BC, DE, HL).
25 n8 8-bit integer constant.
27 n16 16-bit integer constant.
29 e8 8-bit offset (-128 to 127).
31 u3 3-bit unsigned integer constant (0 to 7).
33 cc Condition codes:
35 Z Execute if Z is set.
36 NZ Execute if Z is not set.
37 C Execute if C is set.
38 NC Execute if C is not set.
39 vec One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30
41 and 0x38).
42
44 8-bit Arithmetic and Logic Instructions
45 ADC A,r8
46 ADC A,[HL]
47 ADC A,n8
48 ADD A,r8
49 ADD A,[HL]
50 ADD A,n8
51 AND A,r8
52 AND A,[HL]
53 AND A,n8
54 CP A,r8
55 CP A,[HL]
56 CP A,n8
57 DEC r8
58 DEC [HL]
59 INC r8
60 INC [HL]
61 OR A,r8
62 OR A,[HL]
63 OR A,n8
64 SBC A,r8
65 SBC A,[HL]
66 SBC A,n8
67 SUB A,r8
68 SUB A,[HL]
69 SUB A,n8
70 XOR A,r8
71 XOR A,[HL]
72 XOR A,n8
73 16-bit Arithmetic Instructions
75 ADD HL,r16
76 DEC r16
77 INC r16
78 Bit Operations Instructions
80 BIT u3,r8
81 BIT u3,[HL]
82 RES u3,r8
83 RES u3,[HL]
84 SET u3,r8
85 SET u3,[HL]
86 SWAP r8
87 SWAP [HL]
88 Bit Shift Instructions
90 RL r8
91 RL [HL]
92 RLA
93 RLC r8
94 RLC [HL]
95 RLCA
96 RR r8
97 RR [HL]
98 RRA
99 RRC r8
100 RRC [HL]
101 RRCA
102 SLA r8
103 SLA [HL]
104 SRA r8
105 SRA [HL]
106 SRL r8
107 SRL [HL]
108 Load Instructions
110 LD r8,r8
111 LD r8,n8
112 LD r16,n16
113 LD [HL],r8
114 LD [HL],n8
115 LD r8,[HL]
116 LD [r16],A
117 LD [n16],A
118 LDH [n16],A
119 LDH [C],A
120 LD A,[r16]
121 LD A,[n16]
122 LDH A,[n16]
123 LDH A,[C]
124 LD [HLI],A
125 LD [HLD],A
126 LD A,[HLI]
127 LD A,[HLD]
128 Jumps and Subroutines
130 CALL n16
131 CALL cc,n16
132 JP HL
133 JP n16
134 JP cc,n16
135 JR e8
136 JR cc,e8
137 RET cc
138 RET
139 RETI
140 RST vec
141 Stack Operations Instructions
143 ADD HL,SP
144 ADD SP,e8
145 DEC SP
146 INC SP
147 LD SP,n16
148 LD [n16],SP
149 LD HL,SP+e8
150 LD SP,HL
151 POP AF
152 POP r16
153 PUSH AF
154 PUSH r16
155 Miscellaneous Instructions
157 CCF
158 CPL
159 DAA
160 DI
161 EI
162 HALT
163 NOP
164 SCF
165 STOP
166
168 ADC A,r8
169 Add the value in r8 plus the carry flag to A.
170 Cycles: 1
172 Bytes: 1
174 Flags:
176 Z Set if result is 0.
177 N 0
178 H Set if overflow from bit 3.
179 C Set if overflow from bit 7.
180 ADC A,[HL]
182 Add the byte pointed to by HL plus the carry flag to A.
183 Cycles: 2
185 Bytes: 1
187 Flags: See ADC A,r8
189 ADC A,n8
191 Add the value n8 plus the carry flag to A.
192 Cycles: 2
194 Bytes: 2
196 Flags: See ADC A,r8
198 ADD A,r8
200 Add the value in r8 to A.
201 Cycles: 1
203 Bytes: 1
205 Flags:
207 Z Set if result is 0.
208 N 0
209 H Set if overflow from bit 3.
210 C Set if overflow from bit 7.
211 ADD A,[HL]
213 Add the byte pointed to by HL to A.
214 Cycles: 2
216 Bytes: 1
218 Flags: See ADD A,r8
220 ADD A,n8
222 Add the value n8 to A.
223 Cycles: 2
225 Bytes: 2
227 Flags: See ADD A,r8
229 ADD HL,r16
231 Add the value in r16 to HL.
232 Cycles: 2
234 Bytes: 1
236 Flags:
238 N 0
239 H Set if overflow from bit 11.
240 C Set if overflow from bit 15.
241 ADD HL,SP
243 Add the value in SP to HL.
244 Cycles: 2
246 Bytes: 1
248 Flags: See ADD HL,r16
250 ADD SP,e8
252 Add the signed value e8 to SP.
253 Cycles: 4
255 Bytes: 2
257 Flags:
259 Z 0
260 N 0
261 H Set if overflow from bit 3.
262 C Set if overflow from bit 7.
263 AND A,r8
265 Bitwise AND between the value in r8 and A.
266 Cycles: 1
268 Bytes: 1
270 Flags:
272 Z Set if result is 0.
273 N 0
274 H 1
275 C 0
276 AND A,[HL]
278 Bitwise AND between the byte pointed to by HL and A.
279 Cycles: 2
281 Bytes: 1
283 Flags: See AND A,r8
285 AND A,n8
287 Bitwise AND between the value in n8 and A.
288 Cycles: 2
290 Bytes: 2
292 Flags: See AND A,r8
294 BIT u3,r8
296 Test bit u3 in register r8, set the zero flag if bit not set.
297 Cycles: 2
299 Bytes: 2
301 Flags:
303 Z Set if the selected bit is 0.
304 N 0
305 H 1
306 BIT u3,[HL]
308 Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
309 Cycles: 3
311 Bytes: 2
313 Flags: See BIT u3,r8
315 CALL n16
317 Call address n16. This pushes the address of the instruction after the
318 CALL on the stack, such that RET can pop it later; then, it executes an
319 implicit JP n16.
320 Cycles: 6
322 Bytes: 3
324 Flags: None affected.
326 CALL cc,n16
328 Call address n16 if condition cc is met.
329 Cycles: 6 taken / 3 untaken
331 Bytes: 3
333 Flags: None affected.
335 CCF
337 Complement Carry Flag.
338 Cycles: 1
340 Bytes: 1
342 Flags:
344 N 0
345 H 0
346 C Inverted.
347 CP A,r8
349 Subtract the value in r8 from A and set flags accordingly, but don't
350 store the result. This is useful for ComParing values.
351 Cycles: 1
353 Bytes: 1
355 Flags:
357 Z Set if result is 0.
358 N 1
359 H Set if borrow from bit 4.
360 C Set if borrow (i.e. if r8 > A).
361 CP A,[HL]
363 Subtract the byte pointed to by HL from A and set flags accordingly, but
364 don't store the result.
365 Cycles: 2
367 Bytes: 1
369 Flags: See CP A,r8
371 CP A,n8
373 Subtract the value n8 from A and set flags accordingly, but don't store
374 the result.
375 Cycles: 2
377 Bytes: 2
379 Flags: See CP A,r8
381 CPL
383 ComPLement accumulator (A = ~A).
384 Cycles: 1
386 Bytes: 1
388 Flags:
390 N 1
391 H 1
392 DAA
394 Decimal Adjust Accumulator to get a correct BCD representation after an
395 arithmetic instruction.
396 Cycles: 1
398 Bytes: 1
400 Flags:
402 Z Set if result is 0.
403 H 0
404 C Set or reset depending on the operation.
405 DEC r8
407 Decrement value in register r8 by 1.
408 Cycles: 1
410 Bytes: 1
412 Flags:
414 Z Set if result is 0.
415 N 1
416 H Set if borrow from bit 4.
417 DEC [HL]
419 Decrement the byte pointed to by HL by 1.
420 Cycles: 3
422 Bytes: 1
424 Flags: See DEC r8
426 DEC r16
428 Decrement value in register r16 by 1.
429 Cycles: 2
431 Bytes: 1
433 Flags: None affected.
435 DEC SP
437 Decrement value in register SP by 1.
438 Cycles: 2
440 Bytes: 1
442 Flags: None affected.
444 DI
446 Disable Interrupts by clearing the IME flag.
447 Cycles: 1
449 Bytes: 1
451 Flags: None affected.
453 EI
455 Enable Interrupts by setting the IME flag. The flag is only set after
456 the instruction following EI.
457 Cycles: 1
459 Bytes: 1
461 Flags: None affected.
463 HALT
465 Enter CPU low-power consumption mode until an interrupt occurs. The ex‐
466 act behavior of this instruction depends on the state of the IME flag.
467 IME set
469 The CPU enters low-power mode until after an interrupt is about
470 to be serviced. The handler is executed normally, and the CPU
471 resumes execution after the HALT when that returns.
472 IME not set
474 The behavior depends on whether an interrupt is pending (i.e.
475 ‘[IE] & [IF]’ is non-zero).
476 None pending
478 As soon as an interrupt becomes pending, the CPU resumes
479 execution. This is like the above, except that the han‐
480 dler is not called.
481 Some pending
483 The CPU continues execution after the HALT, but the byte
484 after it is read twice in a row (PC is not incremented,
485 due to a hardware bug).
486 Cycles: -
488 Bytes: 1
490 Flags: None affected.
492 INC r8
494 Increment value in register r8 by 1.
495 Cycles: 1
497 Bytes: 1
499 Flags:
501 Z Set if result is 0.
502 N 0
503 H Set if overflow from bit 3.
504 INC [HL]
506 Increment the byte pointed to by HL by 1.
507 Cycles: 3
509 Bytes: 1
511 Flags: See INC r8
513 INC r16
515 Increment value in register r16 by 1.
516 Cycles: 2
518 Bytes: 1
520 Flags: None affected.
522 INC SP
524 Increment value in register SP by 1.
525 Cycles: 2
527 Bytes: 1
529 Flags: None affected.
531 JP n16
533 Jump to address n16; effectively, store n16 into PC.
534 Cycles: 4
536 Bytes: 3
538 Flags: None affected.
540 JP cc,n16
542 Jump to address n16 if condition cc is met.
543 Cycles: 4 taken / 3 untaken
545 Bytes: 3
547 Flags: None affected.
549 JP HL
551 Jump to address in HL; effectively, load PC with value in register HL.
552 Cycles: 1
554 Bytes: 1
556 Flags: None affected.
558 JR e8
560 Relative Jump by adding e8 to the address of the instruction following
561 the JR. To clarify, an operand of 0 is equivalent to no jumping.
562 Cycles: 3
564 Bytes: 2
566 Flags: None affected.
568 JR cc,e8
570 Relative Jump by adding e8 to the current address if condition cc is met.
571 Cycles: 3 taken / 2 untaken
573 Bytes: 2
575 Flags: None affected.
577 LD r8,r8
579 Load (copy) value in register on the right into register on the left.
580 Cycles: 1
582 Bytes: 1
584 Flags: None affected.
586 LD r8,n8
588 Load value n8 into register r8.
589 Cycles: 2
591 Bytes: 2
593 Flags: None affected.
595 LD r16,n16
597 Load value n16 into register r16.
598 Cycles: 3
600 Bytes: 3
602 Flags: None affected.
604 LD [HL],r8
606 Store value in register r8 into byte pointed to by register HL.
607 Cycles: 2
609 Bytes: 1
611 Flags: None affected.
613 LD [HL],n8
615 Store value n8 into byte pointed to by register HL.
616 Cycles: 3
618 Bytes: 2
620 Flags: None affected.
622 LD r8,[HL]
624 Load value into register r8 from byte pointed to by register HL.
625 Cycles: 2
627 Bytes: 1
629 Flags: None affected.
631 LD [r16],A
633 Store value in register A into byte pointed to by register r16.
634 Cycles: 2
636 Bytes: 1
638 Flags: None affected.
640 LD [n16],A
642 Store value in register A into byte at address n16.
643 Cycles: 4
645 Bytes: 3
647 Flags: None affected.
649 LDH [n16],A
651 Store value in register A into byte at address n16, provided it is be‐
652 tween $FF00 and $FFFF.
653 Cycles: 3
655 Bytes: 2
657 Flags: None affected.
659 This is sometimes written as ‘LDIO [n16],A’, or ‘LD [$FF00+n8],A’.
661 LDH [C],A
663 Store value in register A into byte at address $FF00+C.
664 Cycles: 2
666 Bytes: 1
668 Flags: None affected.
670 This is sometimes written as ‘LDIO [C],A’, or ‘LD [$FF00+C],A’.
672 LD A,[r16]
674 Load value in register A from byte pointed to by register r16.
675 Cycles: 2
677 Bytes: 1
679 Flags: None affected.
681 LD A,[n16]
683 Load value in register A from byte at address n16.
684 Cycles: 4
686 Bytes: 3
688 Flags: None affected.
690 LDH A,[n16]
692 Load value in register A from byte at address n16, provided it is between
693 $FF00 and $FFFF.
694 Cycles: 3
696 Bytes: 2
698 Flags: None affected.
700 This is sometimes written as ‘LDIO A,[n16]’, or ‘LD A,[$FF00+n8]’.
702 LDH A,[C]
704 Load value in register A from byte at address $FF00+c.
705 Cycles: 2
707 Bytes: 1
709 Flags: None affected.
711 This is sometimes written as ‘LDIO A,[C]’, or ‘LD A,[$FF00+C]’.
713 LD [HLI],A
715 Store value in register A into byte pointed by HL and increment HL after‐
716 wards.
717 Cycles: 2
719 Bytes: 1
721 Flags: None affected.
723 This is sometimes written as ‘LD [HL+],A’, or ‘LDI [HL],A’.
725 LD [HLD],A
727 Store value in register A into byte pointed by HL and decrement HL after‐
728 wards.
729 Cycles: 2
731 Bytes: 1
733 Flags: None affected.
735 This is sometimes written as ‘LD [HL-],A’, or ‘LDD [HL],A’.
737 LD A,[HLD]
739 Load value into register A from byte pointed by HL and decrement HL af‐
740 terwards.
741 Cycles: 2
743 Bytes: 1
745 Flags: None affected.
747 This is sometimes written as ‘LD A,[HL-]’, or ‘LDD A,[HL]’.
749 LD A,[HLI]
751 Load value into register A from byte pointed by HL and increment HL af‐
752 terwards.
753 Cycles: 2
755 Bytes: 1
757 Flags: None affected.
759 This is sometimes written as ‘LD A,[HL+],’, or ‘LDI A,[HL]’.
761 LD SP,n16
763 Load value n16 into register SP.
764 Cycles: 3
766 Bytes: 3
768 Flags: None affected.
770 LD [n16],SP
772 Store SP & $FF at address n16 and SP >> 8 at address n16 + 1.
773 Cycles: 5
775 Bytes: 3
777 Flags: None affected.
779 LD HL,SP+e8
781 Add the signed value e8 to SP and store the result in HL.
782 Cycles: 3
784 Bytes: 2
786 Flags:
788 Z 0
789 N 0
790 H Set if overflow from bit 3.
791 C Set if overflow from bit 7.
792 LD SP,HL
794 Load register HL into register SP.
795 Cycles: 2
797 Bytes: 1
799 Flags: None affected.
801 NOP
803 No OPeration.
804 Cycles: 1
806 Bytes: 1
808 Flags: None affected.
810 OR A,r8
812 Store into A the bitwise OR of the value in r8 and A.
813 Cycles: 1
815 Bytes: 1
817 Flags:
819 Z Set if result is 0.
820 N 0
821 H 0
822 C 0
823 OR A,[HL]
825 Store into A the bitwise OR of the byte pointed to by HL and A.
826 Cycles: 2
828 Bytes: 1
830 Flags: See OR A,r8
832 OR A,n8
834 Store into A the bitwise OR of n8 and A.
835 Cycles: 2
837 Bytes: 2
839 Flags: See OR A,r8
841 POP AF
843 Pop register AF from the stack. This is roughly equivalent to the fol‐
844 lowing imaginary instructions:
845 ld f, [sp] ; See below for individual flags
847 inc sp
848 ld a, [sp]
849 inc sp
850 Cycles: 3
852 Bytes: 1
854 Flags:
856 Z Set from bit 7 of the popped low byte.
857 N Set from bit 6 of the popped low byte.
858 H Set from bit 5 of the popped low byte.
859 C Set from bit 4 of the popped low byte.
860 POP r16
862 Pop register r16 from the stack. This is roughly equivalent to the fol‐
863 lowing imaginary instructions:
864 ld LOW(r16), [sp] ; C, E or L
866 inc sp
867 ld HIGH(r16), [sp] ; B, D or H
868 inc sp
869 Cycles: 3
871 Bytes: 1
873 Flags: None affected.
875 PUSH AF
877 Push register AF into the stack. This is roughly equivalent to the fol‐
878 lowing imaginary instructions:
879 dec sp
881 ld [sp], a
882 dec sp
883 ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4
884 Cycles: 4
886 Bytes: 1
888 Flags: None affected.
890 PUSH r16
892 Push register r16 into the stack. This is roughly equivalent to the fol‐
893 lowing imaginary instructions:
894 dec sp
896 ld [sp], HIGH(r16) ; B, D or H
897 dec sp
898 ld [sp], LOW(r16) ; C, E or L
899 Cycles: 4
901 Bytes: 1
903 Flags: None affected.
905 RES u3,r8
907 Set bit u3 in register r8 to 0. Bit 0 is the rightmost one, bit 7 the
908 leftmost one.
909 Cycles: 2
911 Bytes: 2
913 Flags: None affected.
915 RES u3,[HL]
917 Set bit u3 in the byte pointed by HL to 0. Bit 0 is the rightmost one,
918 bit 7 the leftmost one.
919 Cycles: 4
921 Bytes: 2
923 Flags: None affected.
925 RET
927 Return from subroutine. This is basically a POP PC (if such an instruc‐
928 tion existed). See POP r16 for an explanation of how POP works.
929 Cycles: 4
931 Bytes: 1
933 Flags: None affected.
935 RET cc
937 Return from subroutine if condition cc is met.
938 Cycles: 5 taken / 2 untaken
940 Bytes: 1
942 Flags: None affected.
944 RETI
946 Return from subroutine and enable interrupts. This is basically equiva‐
947 lent to executing EI then RET, meaning that IME is set right after this
948 instruction.
949 Cycles: 4
951 Bytes: 1
953 Flags: None affected.
955 RL r8
957 Rotate bits in register r8 left through carry.
958 C <- [7 <- 0] <- C
960 Cycles: 2
962 Bytes: 2
964 Flags:
966 Z Set if result is 0.
967 N 0
968 H 0
969 C Set according to result.
970 RL [HL]
972 Rotate byte pointed to by HL left through carry.
973 C <- [7 <- 0] <- C
975 Cycles: 4
977 Bytes: 2
979 Flags: See RL r8
981 RLA
983 Rotate register A left through carry.
984 C <- [7 <- 0] <- C
986 Cycles: 1
988 Bytes: 1
990 Flags:
992 Z 0
993 N 0
994 H 0
995 C Set according to result.
996 RLC r8
998 Rotate register r8 left.
999 C <- [7 <- 0] <- [7]
1001 Cycles: 2
1003 Bytes: 2
1005 Flags:
1007 Z Set if result is 0.
1008 N 0
1009 H 0
1010 C Set according to result.
1011 RLC [HL]
1013 Rotate byte pointed to by HL left.
1014 C <- [7 <- 0] <- [7]
1016 Cycles: 4
1018 Bytes: 2
1020 Flags: See RLC r8
1022 RLCA
1024 Rotate register A left.
1025 C <- [7 <- 0] <- [7]
1027 Cycles: 1
1029 Bytes: 1
1031 Flags:
1033 Z 0
1034 N 0
1035 H 0
1036 C Set according to result.
1037 RR r8
1039 Rotate register r8 right through carry.
1040 C -> [7 -> 0] -> C
1042 Cycles: 2
1044 Bytes: 2
1046 Flags:
1048 Z Set if result is 0.
1049 N 0
1050 H 0
1051 C Set according to result.
1052 RR [HL]
1054 Rotate byte pointed to by HL right through carry.
1055 C -> [7 -> 0] -> C
1057 Cycles: 4
1059 Bytes: 2
1061 Flags: See RR r8
1063 RRA
1065 Rotate register A right through carry.
1066 C -> [7 -> 0] -> C
1068 Cycles: 1
1070 Bytes: 1
1072 Flags:
1074 Z 0
1075 N 0
1076 H 0
1077 C Set according to result.
1078 RRC r8
1080 Rotate register r8 right.
1081 [0] -> [7 -> 0] -> C
1083 Cycles: 2
1085 Bytes: 2
1087 Flags:
1089 Z Set if result is 0.
1090 N 0
1091 H 0
1092 C Set according to result.
1093 RRC [HL]
1095 Rotate byte pointed to by HL right.
1096 [0] -> [7 -> 0] -> C
1098 Cycles: 4
1100 Bytes: 2
1102 Flags: See RRC r8
1104 RRCA
1106 Rotate register A right.
1107 [0] -> [7 -> 0] -> C
1109 Cycles: 1
1111 Bytes: 1
1113 Flags:
1115 Z 0
1116 N 0
1117 H 0
1118 C Set according to result.
1119 RST vec
1121 Call address vec. This is a shorter and faster equivalent to CALL for
1122 suitable values of vec.
1123 Cycles: 4
1125 Bytes: 1
1127 Flags: None affected.
1129 SBC A,r8
1131 Subtract the value in r8 and the carry flag from A.
1132 Cycles: 1
1134 Bytes: 1
1136 Flags:
1138 Z Set if result is 0.
1139 N 1
1140 H Set if borrow from bit 4.
1141 C Set if borrow (i.e. if (r8 + carry) > A).
1142 SBC A,[HL]
1144 Subtract the byte pointed to by HL and the carry flag from A.
1145 Cycles: 2
1147 Bytes: 1
1149 Flags: See SBC A,r8
1151 SBC A,n8
1153 Subtract the value n8 and the carry flag from A.
1154 Cycles: 2
1156 Bytes: 2
1158 Flags: See SBC A,r8
1160 SCF
1162 Set Carry Flag.
1163 Cycles: 1
1165 Bytes: 1
1167 Flags:
1169 N 0
1170 H 0
1171 C 1
1172 SET u3,r8
1174 Set bit u3 in register r8 to 1. Bit 0 is the rightmost one, bit 7 the
1175 leftmost one.
1176 Cycles: 2
1178 Bytes: 2
1180 Flags: None affected.
1182 SET u3,[HL]
1184 Set bit u3 in the byte pointed by HL to 1. Bit 0 is the rightmost one,
1185 bit 7 the leftmost one.
1186 Cycles: 4
1188 Bytes: 2
1190 Flags: None affected.
1192 SLA r8
1194 Shift Left Arithmetic register r8.
1195 C <- [7 <- 0] <- 0
1197 Cycles: 2
1199 Bytes: 2
1201 Flags:
1203 Z Set if result is 0.
1204 N 0
1205 H 0
1206 C Set according to result.
1207 SLA [HL]
1209 Shift Left Arithmetic byte pointed to by HL.
1210 C <- [7 <- 0] <- 0
1212 Cycles: 4
1214 Bytes: 2
1216 Flags: See SLA r8
1218 SRA r8
1220 Shift Right Arithmetic register r8.
1221 [7] -> [7 -> 0] -> C
1223 Cycles: 2
1225 Bytes: 2
1227 Flags:
1229 Z Set if result is 0.
1230 N 0
1231 H 0
1232 C Set according to result.
1233 SRA [HL]
1235 Shift Right Arithmetic byte pointed to by HL.
1236 [7] -> [7 -> 0] -> C
1238 Cycles: 4
1240 Bytes: 2
1242 Flags: See SRA r8
1244 SRL r8
1246 Shift Right Logic register r8.
1247 0 -> [7 -> 0] -> C
1249 Cycles: 2
1251 Bytes: 2
1253 Flags:
1255 Z Set if result is 0.
1256 N 0
1257 H 0
1258 C Set according to result.
1259 SRL [HL]
1261 Shift Right Logic byte pointed to by HL.
1262 0 -> [7 -> 0] -> C
1264 Cycles: 4
1266 Bytes: 2
1268 Flags: See SRA r8
1270 STOP
1272 Enter CPU very low power mode. Also used to switch between double and
1273 normal speed CPU modes in GBC.
1274 Cycles: -
1276 Bytes: 2
1278 Flags: None affected.
1280 SUB A,r8
1282 Subtract the value in r8 from A.
1283 Cycles: 1
1285 Bytes: 1
1287 Flags:
1289 Z Set if result is 0.
1290 N 1
1291 H Set if borrow from bit 4.
1292 C Set if borrow (set if r8 > A).
1293 SUB A,[HL]
1295 Subtract the byte pointed to by HL from A.
1296 Cycles: 2
1298 Bytes: 1
1300 Flags: See SUB A,r8
1302 SUB A,n8
1304 Subtract the value n8 from A.
1305 Cycles: 2
1307 Bytes: 2
1309 Flags: See SUB A,r8
1311 SWAP r8
1313 Swap upper 4 bits in register r8 and the lower 4 ones.
1314 Cycles: 2
1316 Bytes: 2
1318 Flags:
1320 Z Set if result is 0.
1321 N 0
1322 H 0
1323 C 0
1324 SWAP [HL]
1326 Swap upper 4 bits in the byte pointed by HL and the lower 4 ones.
1327 Cycles: 4
1329 Bytes: 2
1331 Flags: See SWAP r8
1333 XOR A,r8
1335 Bitwise XOR between the value in r8 and A.
1336 Cycles: 1
1338 Bytes: 1
1340 Flags:
1342 Z Set if result is 0.
1343 N 0
1344 H 0
1345 C 0
1346 XOR A,[HL]
1348 Bitwise XOR between the byte pointed to by HL and A.
1349 Cycles: 2
1351 Bytes: 1
1353 Flags: See XOR A,r8
1355 XOR A,n8
1357 Bitwise XOR between the value in n8 and A.
1358 Cycles: 2
1360 Bytes: 2
1362 Flags: See XOR A,r8
1364
1366 rgbasm(1), rgbds(7)
1367
1369 rgbds was originally written by Carsten Sørensen as part of the ASMotor
1370 package, and was later packaged in RGBDS by Justin Lloyd. It is now
1371 maintained by a number of contributors at https://github.com/gbdev/rgbds
1372BSD March 28, 2021 BSD