1GBZ80(7) BSD Miscellaneous Information Manual GBZ80(7)
2
4 gbz80 — CPU opcode reference
5
7 This is the list of opcodes supported by rgbasm(1), including a short de‐
8 scription, the number of bytes needed to encode them and the number of
9 CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10 them.
11 Note: All arithmetic/logic operations that use register A as destination
13 can omit the destination as it is assumed to be register A by default.
14 The following two lines have the same effect:
15 OR A,B
17 OR B
18
20 List of abbreviations used in this document.
21 r8 Any of the 8-bit registers (A, B, C, D, E, H, L).
23 r16 Any of the general-purpose 16-bit registers (BC, DE, HL).
25 n8 8-bit integer constant.
27 n16 16-bit integer constant.
29 e8 8-bit offset (-128 to 127).
31 u3 3-bit unsigned integer constant (0 to 7).
33 cc Condition codes:
35 Z Execute if Z is set.
36 NZ Execute if Z is not set.
37 C Execute if C is set.
38 NC Execute if C is not set.
39 ! cc Negates a condition code.
40 vec One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30,
42 and 0x38).
43
45 8-bit Arithmetic and Logic Instructions
46 ADC A,r8
47 ADC A,[HL]
48 ADC A,n8
49 ADD A,r8
50 ADD A,[HL]
51 ADD A,n8
52 AND A,r8
53 AND A,[HL]
54 AND A,n8
55 CP A,r8
56 CP A,[HL]
57 CP A,n8
58 DEC r8
59 DEC [HL]
60 INC r8
61 INC [HL]
62 OR A,r8
63 OR A,[HL]
64 OR A,n8
65 SBC A,r8
66 SBC A,[HL]
67 SBC A,n8
68 SUB A,r8
69 SUB A,[HL]
70 SUB A,n8
71 XOR A,r8
72 XOR A,[HL]
73 XOR A,n8
74 16-bit Arithmetic Instructions
76 ADD HL,r16
77 DEC r16
78 INC r16
79 Bit Operations Instructions
81 BIT u3,r8
82 BIT u3,[HL]
83 RES u3,r8
84 RES u3,[HL]
85 SET u3,r8
86 SET u3,[HL]
87 SWAP r8
88 SWAP [HL]
89 Bit Shift Instructions
91 RL r8
92 RL [HL]
93 RLA
94 RLC r8
95 RLC [HL]
96 RLCA
97 RR r8
98 RR [HL]
99 RRA
100 RRC r8
101 RRC [HL]
102 RRCA
103 SLA r8
104 SLA [HL]
105 SRA r8
106 SRA [HL]
107 SRL r8
108 SRL [HL]
109 Load Instructions
111 LD r8,r8
112 LD r8,n8
113 LD r16,n16
114 LD [HL],r8
115 LD [HL],n8
116 LD r8,[HL]
117 LD [r16],A
118 LD [n16],A
119 LDH [n16],A
120 LDH [C],A
121 LD A,[r16]
122 LD A,[n16]
123 LDH A,[n16]
124 LDH A,[C]
125 LD [HLI],A
126 LD [HLD],A
127 LD A,[HLI]
128 LD A,[HLD]
129 Jumps and Subroutines
131 CALL n16
132 CALL cc,n16
133 JP HL
134 JP n16
135 JP cc,n16
136 JR e8
137 JR cc,e8
138 RET cc
139 RET
140 RETI
141 RST vec
142 Stack Operations Instructions
144 ADD HL,SP
145 ADD SP,e8
146 DEC SP
147 INC SP
148 LD SP,n16
149 LD [n16],SP
150 LD HL,SP+e8
151 LD SP,HL
152 POP AF
153 POP r16
154 PUSH AF
155 PUSH r16
156 Miscellaneous Instructions
158 CCF
159 CPL
160 DAA
161 DI
162 EI
163 HALT
164 NOP
165 SCF
166 STOP
167
169 ADC A,r8
170 Add the value in r8 plus the carry flag to A.
171 Cycles: 1
173 Bytes: 1
175 Flags:
177 Z Set if result is 0.
178 N 0
179 H Set if overflow from bit 3.
180 C Set if overflow from bit 7.
181 ADC A,[HL]
183 Add the byte pointed to by HL plus the carry flag to A.
184 Cycles: 2
186 Bytes: 1
188 Flags: See ADC A,r8
190 ADC A,n8
192 Add the value n8 plus the carry flag to A.
193 Cycles: 2
195 Bytes: 2
197 Flags: See ADC A,r8
199 ADD A,r8
201 Add the value in r8 to A.
202 Cycles: 1
204 Bytes: 1
206 Flags:
208 Z Set if result is 0.
209 N 0
210 H Set if overflow from bit 3.
211 C Set if overflow from bit 7.
212 ADD A,[HL]
214 Add the byte pointed to by HL to A.
215 Cycles: 2
217 Bytes: 1
219 Flags: See ADD A,r8
221 ADD A,n8
223 Add the value n8 to A.
224 Cycles: 2
226 Bytes: 2
228 Flags: See ADD A,r8
230 ADD HL,r16
232 Add the value in r16 to HL.
233 Cycles: 2
235 Bytes: 1
237 Flags:
239 N 0
240 H Set if overflow from bit 11.
241 C Set if overflow from bit 15.
242 ADD HL,SP
244 Add the value in SP to HL.
245 Cycles: 2
247 Bytes: 1
249 Flags: See ADD HL,r16
251 ADD SP,e8
253 Add the signed value e8 to SP.
254 Cycles: 4
256 Bytes: 2
258 Flags:
260 Z 0
261 N 0
262 H Set if overflow from bit 3.
263 C Set if overflow from bit 7.
264 AND A,r8
266 Bitwise AND between the value in r8 and A.
267 Cycles: 1
269 Bytes: 1
271 Flags:
273 Z Set if result is 0.
274 N 0
275 H 1
276 C 0
277 AND A,[HL]
279 Bitwise AND between the byte pointed to by HL and A.
280 Cycles: 2
282 Bytes: 1
284 Flags: See AND A,r8
286 AND A,n8
288 Bitwise AND between the value in n8 and A.
289 Cycles: 2
291 Bytes: 2
293 Flags: See AND A,r8
295 BIT u3,r8
297 Test bit u3 in register r8, set the zero flag if bit not set.
298 Cycles: 2
300 Bytes: 2
302 Flags:
304 Z Set if the selected bit is 0.
305 N 0
306 H 1
307 BIT u3,[HL]
309 Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
310 Cycles: 3
312 Bytes: 2
314 Flags: See BIT u3,r8
316 CALL n16
318 Call address n16. This pushes the address of the instruction after the
319 CALL on the stack, such that RET can pop it later; then, it executes an
320 implicit JP n16.
321 Cycles: 6
323 Bytes: 3
325 Flags: None affected.
327 CALL cc,n16
329 Call address n16 if condition cc is met.
330 Cycles: 6 taken / 3 untaken
332 Bytes: 3
334 Flags: None affected.
336 CCF
338 Complement Carry Flag.
339 Cycles: 1
341 Bytes: 1
343 Flags:
345 N 0
346 H 0
347 C Inverted.
348 CP A,r8
350 Subtract the value in r8 from A and set flags accordingly, but don't
351 store the result. This is useful for ComParing values.
352 Cycles: 1
354 Bytes: 1
356 Flags:
358 Z Set if result is 0.
359 N 1
360 H Set if borrow from bit 4.
361 C Set if borrow (i.e. if r8 > A).
362 CP A,[HL]
364 Subtract the byte pointed to by HL from A and set flags accordingly, but
365 don't store the result.
366 Cycles: 2
368 Bytes: 1
370 Flags: See CP A,r8
372 CP A,n8
374 Subtract the value n8 from A and set flags accordingly, but don't store
375 the result.
376 Cycles: 2
378 Bytes: 2
380 Flags: See CP A,r8
382 CPL
384 ComPLement accumulator (A = ~A).
385 Cycles: 1
387 Bytes: 1
389 Flags:
391 N 1
392 H 1
393 DAA
395 Decimal Adjust Accumulator to get a correct BCD representation after an
396 arithmetic instruction.
397 Cycles: 1
399 Bytes: 1
401 Flags:
403 Z Set if result is 0.
404 H 0
405 C Set or reset depending on the operation.
406 DEC r8
408 Decrement value in register r8 by 1.
409 Cycles: 1
411 Bytes: 1
413 Flags:
415 Z Set if result is 0.
416 N 1
417 H Set if borrow from bit 4.
418 DEC [HL]
420 Decrement the byte pointed to by HL by 1.
421 Cycles: 3
423 Bytes: 1
425 Flags: See DEC r8
427 DEC r16
429 Decrement value in register r16 by 1.
430 Cycles: 2
432 Bytes: 1
434 Flags: None affected.
436 DEC SP
438 Decrement value in register SP by 1.
439 Cycles: 2
441 Bytes: 1
443 Flags: None affected.
445 DI
447 Disable Interrupts by clearing the IME flag.
448 Cycles: 1
450 Bytes: 1
452 Flags: None affected.
454 EI
456 Enable Interrupts by setting the IME flag. The flag is only set after
457 the instruction following EI.
458 Cycles: 1
460 Bytes: 1
462 Flags: None affected.
464 HALT
466 Enter CPU low-power consumption mode until an interrupt occurs. The ex‐
467 act behavior of this instruction depends on the state of the IME flag.
468 IME set
470 The CPU enters low-power mode until after an interrupt is about
471 to be serviced. The handler is executed normally, and the CPU
472 resumes execution after the HALT when that returns.
473 IME not set
475 The behavior depends on whether an interrupt is pending (i.e.
476 ‘[IE] & [IF]’ is non-zero).
477 None pending
479 As soon as an interrupt becomes pending, the CPU resumes
480 execution. This is like the above, except that the han‐
481 dler is not called.
482 Some pending
484 The CPU continues execution after the HALT, but the byte
485 after it is read twice in a row (PC is not incremented,
486 due to a hardware bug).
487 Cycles: -
489 Bytes: 1
491 Flags: None affected.
493 INC r8
495 Increment value in register r8 by 1.
496 Cycles: 1
498 Bytes: 1
500 Flags:
502 Z Set if result is 0.
503 N 0
504 H Set if overflow from bit 3.
505 INC [HL]
507 Increment the byte pointed to by HL by 1.
508 Cycles: 3
510 Bytes: 1
512 Flags: See INC r8
514 INC r16
516 Increment value in register r16 by 1.
517 Cycles: 2
519 Bytes: 1
521 Flags: None affected.
523 INC SP
525 Increment value in register SP by 1.
526 Cycles: 2
528 Bytes: 1
530 Flags: None affected.
532 JP n16
534 Jump to address n16; effectively, store n16 into PC.
535 Cycles: 4
537 Bytes: 3
539 Flags: None affected.
541 JP cc,n16
543 Jump to address n16 if condition cc is met.
544 Cycles: 4 taken / 3 untaken
546 Bytes: 3
548 Flags: None affected.
550 JP HL
552 Jump to address in HL; effectively, load PC with value in register HL.
553 Cycles: 1
555 Bytes: 1
557 Flags: None affected.
559 JR e8
561 Relative Jump by adding e8 to the address of the instruction following
562 the JR. To clarify, an operand of 0 is equivalent to no jumping.
563 Cycles: 3
565 Bytes: 2
567 Flags: None affected.
569 JR cc,e8
571 Relative Jump by adding e8 to the current address if condition cc is met.
572 Cycles: 3 taken / 2 untaken
574 Bytes: 2
576 Flags: None affected.
578 LD r8,r8
580 Load (copy) value in register on the right into register on the left.
581 Cycles: 1
583 Bytes: 1
585 Flags: None affected.
587 LD r8,n8
589 Load value n8 into register r8.
590 Cycles: 2
592 Bytes: 2
594 Flags: None affected.
596 LD r16,n16
598 Load value n16 into register r16.
599 Cycles: 3
601 Bytes: 3
603 Flags: None affected.
605 LD [HL],r8
607 Store value in register r8 into the byte pointed to by register HL.
608 Cycles: 2
610 Bytes: 1
612 Flags: None affected.
614 LD [HL],n8
616 Store value n8 into the byte pointed to by register HL.
617 Cycles: 3
619 Bytes: 2
621 Flags: None affected.
623 LD r8,[HL]
625 Load value into register r8 from the byte pointed to by register HL.
626 Cycles: 2
628 Bytes: 1
630 Flags: None affected.
632 LD [r16],A
634 Store value in register A into the byte pointed to by register r16.
635 Cycles: 2
637 Bytes: 1
639 Flags: None affected.
641 LD [n16],A
643 Store value in register A into the byte at address n16.
644 Cycles: 4
646 Bytes: 3
648 Flags: None affected.
650 LDH [n16],A
652 Store value in register A into the byte at address n16, provided the ad‐
653 dress is between $FF00 and $FFFF.
654 Cycles: 3
656 Bytes: 2
658 Flags: None affected.
660 This is sometimes written as ‘LDIO [n16],A’, or ‘LD [$FF00+n8],A’.
662 LDH [C],A
664 Store value in register A into the byte at address $FF00+C.
665 Cycles: 2
667 Bytes: 1
669 Flags: None affected.
671 This is sometimes written as ‘LDIO [C],A’, or ‘LD [$FF00+C],A’.
673 LD A,[r16]
675 Load value in register A from the byte pointed to by register r16.
676 Cycles: 2
678 Bytes: 1
680 Flags: None affected.
682 LD A,[n16]
684 Load value in register A from the byte at address n16.
685 Cycles: 4
687 Bytes: 3
689 Flags: None affected.
691 LDH A,[n16]
693 Load value in register A from the byte at address n16, provided the ad‐
694 dress is between $FF00 and $FFFF.
695 Cycles: 3
697 Bytes: 2
699 Flags: None affected.
701 This is sometimes written as ‘LDIO A,[n16]’, or ‘LD A,[$FF00+n8]’.
703 LDH A,[C]
705 Load value in register A from the byte at address $FF00+c.
706 Cycles: 2
708 Bytes: 1
710 Flags: None affected.
712 This is sometimes written as ‘LDIO A,[C]’, or ‘LD A,[$FF00+C]’.
714 LD [HLI],A
716 Store value in register A into the byte pointed by HL and increment HL
717 afterwards.
718 Cycles: 2
720 Bytes: 1
722 Flags: None affected.
724 This is sometimes written as ‘LD [HL+],A’, or ‘LDI [HL],A’.
726 LD [HLD],A
728 Store value in register A into the byte pointed by HL and decrement HL
729 afterwards.
730 Cycles: 2
732 Bytes: 1
734 Flags: None affected.
736 This is sometimes written as ‘LD [HL-],A’, or ‘LDD [HL],A’.
738 LD A,[HLD]
740 Load value into register A from the byte pointed by HL and decrement HL
741 afterwards.
742 Cycles: 2
744 Bytes: 1
746 Flags: None affected.
748 This is sometimes written as ‘LD A,[HL-]’, or ‘LDD A,[HL]’.
750 LD A,[HLI]
752 Load value into register A from the byte pointed by HL and increment HL
753 afterwards.
754 Cycles: 2
756 Bytes: 1
758 Flags: None affected.
760 This is sometimes written as ‘LD A,[HL+]’, or ‘LDI A,[HL]’.
762 LD SP,n16
764 Load value n16 into register SP.
765 Cycles: 3
767 Bytes: 3
769 Flags: None affected.
771 LD [n16],SP
773 Store SP & $FF at address n16 and SP >> 8 at address n16 + 1.
774 Cycles: 5
776 Bytes: 3
778 Flags: None affected.
780 LD HL,SP+e8
782 Add the signed value e8 to SP and store the result in HL.
783 Cycles: 3
785 Bytes: 2
787 Flags:
789 Z 0
790 N 0
791 H Set if overflow from bit 3.
792 C Set if overflow from bit 7.
793 LD SP,HL
795 Load register HL into register SP.
796 Cycles: 2
798 Bytes: 1
800 Flags: None affected.
802 NOP
804 No OPeration.
805 Cycles: 1
807 Bytes: 1
809 Flags: None affected.
811 OR A,r8
813 Store into A the bitwise OR of the value in r8 and A.
814 Cycles: 1
816 Bytes: 1
818 Flags:
820 Z Set if result is 0.
821 N 0
822 H 0
823 C 0
824 OR A,[HL]
826 Store into A the bitwise OR of the byte pointed to by HL and A.
827 Cycles: 2
829 Bytes: 1
831 Flags: See OR A,r8
833 OR A,n8
835 Store into A the bitwise OR of n8 and A.
836 Cycles: 2
838 Bytes: 2
840 Flags: See OR A,r8
842 POP AF
844 Pop register AF from the stack. This is roughly equivalent to the fol‐
845 lowing imaginary instructions:
846 ld f, [sp] ; See below for individual flags
848 inc sp
849 ld a, [sp]
850 inc sp
851 Cycles: 3
853 Bytes: 1
855 Flags:
857 Z Set from bit 7 of the popped low byte.
858 N Set from bit 6 of the popped low byte.
859 H Set from bit 5 of the popped low byte.
860 C Set from bit 4 of the popped low byte.
861 POP r16
863 Pop register r16 from the stack. This is roughly equivalent to the fol‐
864 lowing imaginary instructions:
865 ld LOW(r16), [sp] ; C, E or L
867 inc sp
868 ld HIGH(r16), [sp] ; B, D or H
869 inc sp
870 Cycles: 3
872 Bytes: 1
874 Flags: None affected.
876 PUSH AF
878 Push register AF into the stack. This is roughly equivalent to the fol‐
879 lowing imaginary instructions:
880 dec sp
882 ld [sp], a
883 dec sp
884 ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4
885 Cycles: 4
887 Bytes: 1
889 Flags: None affected.
891 PUSH r16
893 Push register r16 into the stack. This is roughly equivalent to the fol‐
894 lowing imaginary instructions:
895 dec sp
897 ld [sp], HIGH(r16) ; B, D or H
898 dec sp
899 ld [sp], LOW(r16) ; C, E or L
900 Cycles: 4
902 Bytes: 1
904 Flags: None affected.
906 RES u3,r8
908 Set bit u3 in register r8 to 0. Bit 0 is the rightmost one, bit 7 the
909 leftmost one.
910 Cycles: 2
912 Bytes: 2
914 Flags: None affected.
916 RES u3,[HL]
918 Set bit u3 in the byte pointed by HL to 0. Bit 0 is the rightmost one,
919 bit 7 the leftmost one.
920 Cycles: 4
922 Bytes: 2
924 Flags: None affected.
926 RET
928 Return from subroutine. This is basically a POP PC (if such an instruc‐
929 tion existed). See POP r16 for an explanation of how POP works.
930 Cycles: 4
932 Bytes: 1
934 Flags: None affected.
936 RET cc
938 Return from subroutine if condition cc is met.
939 Cycles: 5 taken / 2 untaken
941 Bytes: 1
943 Flags: None affected.
945 RETI
947 Return from subroutine and enable interrupts. This is basically equiva‐
948 lent to executing EI then RET, meaning that IME is set right after this
949 instruction.
950 Cycles: 4
952 Bytes: 1
954 Flags: None affected.
956 RL r8
958 Rotate bits in register r8 left through carry.
959 C <- [7 <- 0] <- C
961 Cycles: 2
963 Bytes: 2
965 Flags:
967 Z Set if result is 0.
968 N 0
969 H 0
970 C Set according to result.
971 RL [HL]
973 Rotate the byte pointed to by HL left through carry.
974 C <- [7 <- 0] <- C
976 Cycles: 4
978 Bytes: 2
980 Flags: See RL r8
982 RLA
984 Rotate register A left through carry.
985 C <- [7 <- 0] <- C
987 Cycles: 1
989 Bytes: 1
991 Flags:
993 Z 0
994 N 0
995 H 0
996 C Set according to result.
997 RLC r8
999 Rotate register r8 left.
1000 C <- [7 <- 0] <- [7]
1002 Cycles: 2
1004 Bytes: 2
1006 Flags:
1008 Z Set if result is 0.
1009 N 0
1010 H 0
1011 C Set according to result.
1012 RLC [HL]
1014 Rotate the byte pointed to by HL left.
1015 C <- [7 <- 0] <- [7]
1017 Cycles: 4
1019 Bytes: 2
1021 Flags: See RLC r8
1023 RLCA
1025 Rotate register A left.
1026 C <- [7 <- 0] <- [7]
1028 Cycles: 1
1030 Bytes: 1
1032 Flags:
1034 Z 0
1035 N 0
1036 H 0
1037 C Set according to result.
1038 RR r8
1040 Rotate register r8 right through carry.
1041 C -> [7 -> 0] -> C
1043 Cycles: 2
1045 Bytes: 2
1047 Flags:
1049 Z Set if result is 0.
1050 N 0
1051 H 0
1052 C Set according to result.
1053 RR [HL]
1055 Rotate the byte pointed to by HL right through carry.
1056 C -> [7 -> 0] -> C
1058 Cycles: 4
1060 Bytes: 2
1062 Flags: See RR r8
1064 RRA
1066 Rotate register A right through carry.
1067 C -> [7 -> 0] -> C
1069 Cycles: 1
1071 Bytes: 1
1073 Flags:
1075 Z 0
1076 N 0
1077 H 0
1078 C Set according to result.
1079 RRC r8
1081 Rotate register r8 right.
1082 [0] -> [7 -> 0] -> C
1084 Cycles: 2
1086 Bytes: 2
1088 Flags:
1090 Z Set if result is 0.
1091 N 0
1092 H 0
1093 C Set according to result.
1094 RRC [HL]
1096 Rotate the byte pointed to by HL right.
1097 [0] -> [7 -> 0] -> C
1099 Cycles: 4
1101 Bytes: 2
1103 Flags: See RRC r8
1105 RRCA
1107 Rotate register A right.
1108 [0] -> [7 -> 0] -> C
1110 Cycles: 1
1112 Bytes: 1
1114 Flags:
1116 Z 0
1117 N 0
1118 H 0
1119 C Set according to result.
1120 RST vec
1122 Call address vec. This is a shorter and faster equivalent to CALL for
1123 suitable values of vec.
1124 Cycles: 4
1126 Bytes: 1
1128 Flags: None affected.
1130 SBC A,r8
1132 Subtract the value in r8 and the carry flag from A.
1133 Cycles: 1
1135 Bytes: 1
1137 Flags:
1139 Z Set if result is 0.
1140 N 1
1141 H Set if borrow from bit 4.
1142 C Set if borrow (i.e. if (r8 + carry) > A).
1143 SBC A,[HL]
1145 Subtract the byte pointed to by HL and the carry flag from A.
1146 Cycles: 2
1148 Bytes: 1
1150 Flags: See SBC A,r8
1152 SBC A,n8
1154 Subtract the value n8 and the carry flag from A.
1155 Cycles: 2
1157 Bytes: 2
1159 Flags: See SBC A,r8
1161 SCF
1163 Set Carry Flag.
1164 Cycles: 1
1166 Bytes: 1
1168 Flags:
1170 N 0
1171 H 0
1172 C 1
1173 SET u3,r8
1175 Set bit u3 in register r8 to 1. Bit 0 is the rightmost one, bit 7 the
1176 leftmost one.
1177 Cycles: 2
1179 Bytes: 2
1181 Flags: None affected.
1183 SET u3,[HL]
1185 Set bit u3 in the byte pointed by HL to 1. Bit 0 is the rightmost one,
1186 bit 7 the leftmost one.
1187 Cycles: 4
1189 Bytes: 2
1191 Flags: None affected.
1193 SLA r8
1195 Shift Left Arithmetically register r8.
1196 C <- [7 <- 0] <- 0
1198 Cycles: 2
1200 Bytes: 2
1202 Flags:
1204 Z Set if result is 0.
1205 N 0
1206 H 0
1207 C Set according to result.
1208 SLA [HL]
1210 Shift Left Arithmetically the byte pointed to by HL.
1211 C <- [7 <- 0] <- 0
1213 Cycles: 4
1215 Bytes: 2
1217 Flags: See SLA r8
1219 SRA r8
1221 Shift Right Arithmetically register r8.
1222 [7] -> [7 -> 0] -> C
1224 Cycles: 2
1226 Bytes: 2
1228 Flags:
1230 Z Set if result is 0.
1231 N 0
1232 H 0
1233 C Set according to result.
1234 SRA [HL]
1236 Shift Right Arithmetically the byte pointed to by HL.
1237 [7] -> [7 -> 0] -> C
1239 Cycles: 4
1241 Bytes: 2
1243 Flags: See SRA r8
1245 SRL r8
1247 Shift Right Logically register r8.
1248 0 -> [7 -> 0] -> C
1250 Cycles: 2
1252 Bytes: 2
1254 Flags:
1256 Z Set if result is 0.
1257 N 0
1258 H 0
1259 C Set according to result.
1260 SRL [HL]
1262 Shift Right Logically the byte pointed to by HL.
1263 0 -> [7 -> 0] -> C
1265 Cycles: 4
1267 Bytes: 2
1269 Flags: See SRA r8
1271 STOP
1273 Enter CPU very low power mode. Also used to switch between double and
1274 normal speed CPU modes in GBC.
1275 Cycles: -
1277 Bytes: 2
1279 Flags: None affected.
1281 SUB A,r8
1283 Subtract the value in r8 from A.
1284 Cycles: 1
1286 Bytes: 1
1288 Flags:
1290 Z Set if result is 0.
1291 N 1
1292 H Set if borrow from bit 4.
1293 C Set if borrow (set if r8 > A).
1294 SUB A,[HL]
1296 Subtract the byte pointed to by HL from A.
1297 Cycles: 2
1299 Bytes: 1
1301 Flags: See SUB A,r8
1303 SUB A,n8
1305 Subtract the value n8 from A.
1306 Cycles: 2
1308 Bytes: 2
1310 Flags: See SUB A,r8
1312 SWAP r8
1314 Swap the upper 4 bits in register r8 and the lower 4 ones.
1315 Cycles: 2
1317 Bytes: 2
1319 Flags:
1321 Z Set if result is 0.
1322 N 0
1323 H 0
1324 C 0
1325 SWAP [HL]
1327 Swap the upper 4 bits in the byte pointed by HL and the lower 4 ones.
1328 Cycles: 4
1330 Bytes: 2
1332 Flags: See SWAP r8
1334 XOR A,r8
1336 Bitwise XOR between the value in r8 and A.
1337 Cycles: 1
1339 Bytes: 1
1341 Flags:
1343 Z Set if result is 0.
1344 N 0
1345 H 0
1346 C 0
1347 XOR A,[HL]
1349 Bitwise XOR between the byte pointed to by HL and A.
1350 Cycles: 2
1352 Bytes: 1
1354 Flags: See XOR A,r8
1356 XOR A,n8
1358 Bitwise XOR between the value in n8 and A.
1359 Cycles: 2
1361 Bytes: 2
1363 Flags: See XOR A,r8
1365
1367 rgbasm(1), rgbds(7)
1368
1370 rgbds was originally written by Carsten Sørensen as part of the ASMotor
1371 package, and was later packaged in RGBDS by Justin Lloyd. It is now
1372 maintained by a number of contributors at https://github.com/gbdev/rgbds
1373BSD March 28, 2021 BSD