1GBZ80(7) BSD Miscellaneous Information Manual GBZ80(7)
2
4 gbz80 — CPU opcode reference
5
7 This is the list of opcodes supported by rgbasm(1), including a short de‐
8 scription, the number of bytes needed to encode them and the number of
9 CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10 them.
11 Note: All arithmetic/logic operations that use register A as destination
13 can omit the destination as it is assumed to be register A by default.
14 The following two lines have the same effect:
15 OR A,B
17 OR B
18
20 List of abbreviations used in this document.
21 r8 Any of the 8-bit registers (A, B, C, D, E, H, L).
23 r16 Any of the general-purpose 16-bit registers (BC, DE, HL).
25 n8 8-bit integer constant.
27 n16 16-bit integer constant.
29 e8 8-bit offset (-128 to 127).
31 u3 3-bit unsigned integer constant (0 to 7).
33 cc Condition codes:
35 Z Execute if Z is set.
36 NZ Execute if Z is not set.
37 C Execute if C is set.
38 NC Execute if C is not set.
39 ! cc Negates a condition code.
40 vec One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30,
42 and 0x38).
43
45 8-bit Arithmetic and Logic Instructions
46 ADC A,r8
47 ADC A,[HL]
48 ADC A,n8
49 ADD A,r8
50 ADD A,[HL]
51 ADD A,n8
52 AND A,r8
53 AND A,[HL]
54 AND A,n8
55 CP A,r8
56 CP A,[HL]
57 CP A,n8
58 DEC r8
59 DEC [HL]
60 INC r8
61 INC [HL]
62 OR A,r8
63 OR A,[HL]
64 OR A,n8
65 SBC A,r8
66 SBC A,[HL]
67 SBC A,n8
68 SUB A,r8
69 SUB A,[HL]
70 SUB A,n8
71 XOR A,r8
72 XOR A,[HL]
73 XOR A,n8
74 16-bit Arithmetic Instructions
76 ADD HL,r16
77 DEC r16
78 INC r16
79 Bit Operations Instructions
81 BIT u3,r8
82 BIT u3,[HL]
83 RES u3,r8
84 RES u3,[HL]
85 SET u3,r8
86 SET u3,[HL]
87 SWAP r8
88 SWAP [HL]
89 Bit Shift Instructions
91 RL r8
92 RL [HL]
93 RLA
94 RLC r8
95 RLC [HL]
96 RLCA
97 RR r8
98 RR [HL]
99 RRA
100 RRC r8
101 RRC [HL]
102 RRCA
103 SLA r8
104 SLA [HL]
105 SRA r8
106 SRA [HL]
107 SRL r8
108 SRL [HL]
109 Load Instructions
111 LD r8,r8
112 LD r8,n8
113 LD r16,n16
114 LD [HL],r8
115 LD [HL],n8
116 LD r8,[HL]
117 LD [r16],A
118 LD [n16],A
119 LDH [n16],A
120 LDH [C],A
121 LD A,[r16]
122 LD A,[n16]
123 LDH A,[n16]
124 LDH A,[C]
125 LD [HLI],A
126 LD [HLD],A
127 LD A,[HLI]
128 LD A,[HLD]
129 Jumps and Subroutines
131 CALL n16
132 CALL cc,n16
133 JP HL
134 JP n16
135 JP cc,n16
136 JR n16
137 JR cc,n16
138 RET cc
139 RET
140 RETI
141 RST vec
142 Stack Operations Instructions
144 ADD HL,SP
145 ADD SP,e8
146 DEC SP
147 INC SP
148 LD SP,n16
149 LD [n16],SP
150 LD HL,SP+e8
151 LD SP,HL
152 POP AF
153 POP r16
154 PUSH AF
155 PUSH r16
156 Miscellaneous Instructions
158 CCF
159 CPL
160 DAA
161 DI
162 EI
163 HALT
164 NOP
165 SCF
166 STOP
167
169 ADC A,r8
170 Add the value in r8 plus the carry flag to A.
171 Cycles: 1
173 Bytes: 1
175 Flags:
177 Z Set if result is 0.
178 N 0
179 H Set if overflow from bit 3.
180 C Set if overflow from bit 7.
181 ADC A,[HL]
183 Add the byte pointed to by HL plus the carry flag to A.
184 Cycles: 2
186 Bytes: 1
188 Flags: See ADC A,r8
190 ADC A,n8
192 Add the value n8 plus the carry flag to A.
193 Cycles: 2
195 Bytes: 2
197 Flags: See ADC A,r8
199 ADD A,r8
201 Add the value in r8 to A.
202 Cycles: 1
204 Bytes: 1
206 Flags:
208 Z Set if result is 0.
209 N 0
210 H Set if overflow from bit 3.
211 C Set if overflow from bit 7.
212 ADD A,[HL]
214 Add the byte pointed to by HL to A.
215 Cycles: 2
217 Bytes: 1
219 Flags: See ADD A,r8
221 ADD A,n8
223 Add the value n8 to A.
224 Cycles: 2
226 Bytes: 2
228 Flags: See ADD A,r8
230 ADD HL,r16
232 Add the value in r16 to HL.
233 Cycles: 2
235 Bytes: 1
237 Flags:
239 N 0
240 H Set if overflow from bit 11.
241 C Set if overflow from bit 15.
242 ADD HL,SP
244 Add the value in SP to HL.
245 Cycles: 2
247 Bytes: 1
249 Flags: See ADD HL,r16
251 ADD SP,e8
253 Add the signed value e8 to SP.
254 Cycles: 4
256 Bytes: 2
258 Flags:
260 Z 0
261 N 0
262 H Set if overflow from bit 3.
263 C Set if overflow from bit 7.
264 AND A,r8
266 Bitwise AND between the value in r8 and A.
267 Cycles: 1
269 Bytes: 1
271 Flags:
273 Z Set if result is 0.
274 N 0
275 H 1
276 C 0
277 AND A,[HL]
279 Bitwise AND between the byte pointed to by HL and A.
280 Cycles: 2
282 Bytes: 1
284 Flags: See AND A,r8
286 AND A,n8
288 Bitwise AND between the value in n8 and A.
289 Cycles: 2
291 Bytes: 2
293 Flags: See AND A,r8
295 BIT u3,r8
297 Test bit u3 in register r8, set the zero flag if bit not set.
298 Cycles: 2
300 Bytes: 2
302 Flags:
304 Z Set if the selected bit is 0.
305 N 0
306 H 1
307 BIT u3,[HL]
309 Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
310 Cycles: 3
312 Bytes: 2
314 Flags: See BIT u3,r8
316 CALL n16
318 Call address n16. This pushes the address of the instruction after the
319 CALL on the stack, such that RET can pop it later; then, it executes an
320 implicit JP n16.
321 Cycles: 6
323 Bytes: 3
325 Flags: None affected.
327 CALL cc,n16
329 Call address n16 if condition cc is met.
330 Cycles: 6 taken / 3 untaken
332 Bytes: 3
334 Flags: None affected.
336 CCF
338 Complement Carry Flag.
339 Cycles: 1
341 Bytes: 1
343 Flags:
345 N 0
346 H 0
347 C Inverted.
348 CP A,r8
350 Subtract the value in r8 from A and set flags accordingly, but don't
351 store the result. This is useful for ComParing values.
352 Cycles: 1
354 Bytes: 1
356 Flags:
358 Z Set if result is 0.
359 N 1
360 H Set if borrow from bit 4.
361 C Set if borrow (i.e. if r8 > A).
362 CP A,[HL]
364 Subtract the byte pointed to by HL from A and set flags accordingly, but
365 don't store the result.
366 Cycles: 2
368 Bytes: 1
370 Flags: See CP A,r8
372 CP A,n8
374 Subtract the value n8 from A and set flags accordingly, but don't store
375 the result.
376 Cycles: 2
378 Bytes: 2
380 Flags: See CP A,r8
382 CPL
384 ComPLement accumulator (A = ~A).
385 Cycles: 1
387 Bytes: 1
389 Flags:
391 N 1
392 H 1
393 DAA
395 Decimal Adjust Accumulator to get a correct BCD representation after an
396 arithmetic instruction.
397 Cycles: 1
399 Bytes: 1
401 Flags:
403 Z Set if result is 0.
404 H 0
405 C Set or reset depending on the operation.
406 DEC r8
408 Decrement value in register r8 by 1.
409 Cycles: 1
411 Bytes: 1
413 Flags:
415 Z Set if result is 0.
416 N 1
417 H Set if borrow from bit 4.
418 DEC [HL]
420 Decrement the byte pointed to by HL by 1.
421 Cycles: 3
423 Bytes: 1
425 Flags: See DEC r8
427 DEC r16
429 Decrement value in register r16 by 1.
430 Cycles: 2
432 Bytes: 1
434 Flags: None affected.
436 DEC SP
438 Decrement value in register SP by 1.
439 Cycles: 2
441 Bytes: 1
443 Flags: None affected.
445 DI
447 Disable Interrupts by clearing the IME flag.
448 Cycles: 1
450 Bytes: 1
452 Flags: None affected.
454 EI
456 Enable Interrupts by setting the IME flag. The flag is only set after
457 the instruction following EI.
458 Cycles: 1
460 Bytes: 1
462 Flags: None affected.
464 HALT
466 Enter CPU low-power consumption mode until an interrupt occurs. The ex‐
467 act behavior of this instruction depends on the state of the IME flag.
468 IME set
470 The CPU enters low-power mode until after an interrupt is about
471 to be serviced. The handler is executed normally, and the CPU
472 resumes execution after the HALT when that returns.
473 IME not set
475 The behavior depends on whether an interrupt is pending (i.e.
476 ‘[IE] & [IF]’ is non-zero).
477 None pending
479 As soon as an interrupt becomes pending, the CPU resumes
480 execution. This is like the above, except that the han‐
481 dler is not called.
482 Some pending
484 The CPU continues execution after the HALT, but the byte
485 after it is read twice in a row (PC is not incremented,
486 due to a hardware bug).
487 Cycles: -
489 Bytes: 1
491 Flags: None affected.
493 INC r8
495 Increment value in register r8 by 1.
496 Cycles: 1
498 Bytes: 1
500 Flags:
502 Z Set if result is 0.
503 N 0
504 H Set if overflow from bit 3.
505 INC [HL]
507 Increment the byte pointed to by HL by 1.
508 Cycles: 3
510 Bytes: 1
512 Flags: See INC r8
514 INC r16
516 Increment value in register r16 by 1.
517 Cycles: 2
519 Bytes: 1
521 Flags: None affected.
523 INC SP
525 Increment value in register SP by 1.
526 Cycles: 2
528 Bytes: 1
530 Flags: None affected.
532 JP n16
534 Jump to address n16; effectively, store n16 into PC.
535 Cycles: 4
537 Bytes: 3
539 Flags: None affected.
541 JP cc,n16
543 Jump to address n16 if condition cc is met.
544 Cycles: 4 taken / 3 untaken
546 Bytes: 3
548 Flags: None affected.
550 JP HL
552 Jump to address in HL; effectively, load PC with value in register HL.
553 Cycles: 1
555 Bytes: 1
557 Flags: None affected.
559 JR n16
561 Relative Jump to address n16. The address is encoded as a signed 8-bit
562 offset from the address immediately following the JR instruction, so the
563 target address n16 must be between -128 and 127 bytes away. For example:
564 JR Label ; no-op; encoded offset of 0
566 Label:
567 JR Label ; infinite loop; encoded offset of -2
568 Cycles: 3
570 Bytes: 2
572 Flags: None affected.
574 JR cc,n16
576 Relative Jump to address n16 if condition cc is met.
577 Cycles: 3 taken / 2 untaken
579 Bytes: 2
581 Flags: None affected.
583 LD r8,r8
585 Load (copy) value in register on the right into register on the left.
586 Cycles: 1
588 Bytes: 1
590 Flags: None affected.
592 LD r8,n8
594 Load value n8 into register r8.
595 Cycles: 2
597 Bytes: 2
599 Flags: None affected.
601 LD r16,n16
603 Load value n16 into register r16.
604 Cycles: 3
606 Bytes: 3
608 Flags: None affected.
610 LD [HL],r8
612 Store value in register r8 into the byte pointed to by register HL.
613 Cycles: 2
615 Bytes: 1
617 Flags: None affected.
619 LD [HL],n8
621 Store value n8 into the byte pointed to by register HL.
622 Cycles: 3
624 Bytes: 2
626 Flags: None affected.
628 LD r8,[HL]
630 Load value into register r8 from the byte pointed to by register HL.
631 Cycles: 2
633 Bytes: 1
635 Flags: None affected.
637 LD [r16],A
639 Store value in register A into the byte pointed to by register r16.
640 Cycles: 2
642 Bytes: 1
644 Flags: None affected.
646 LD [n16],A
648 Store value in register A into the byte at address n16.
649 Cycles: 4
651 Bytes: 3
653 Flags: None affected.
655 LDH [n16],A
657 Store value in register A into the byte at address n16, provided the ad‐
658 dress is between $FF00 and $FFFF.
659 Cycles: 3
661 Bytes: 2
663 Flags: None affected.
665 This is sometimes written as ‘LDIO [n16],A’, or ‘LD [$FF00+n8],A’.
667 LDH [C],A
669 Store value in register A into the byte at address $FF00+C.
670 Cycles: 2
672 Bytes: 1
674 Flags: None affected.
676 This is sometimes written as ‘LDIO [C],A’, or ‘LD [$FF00+C],A’.
678 LD A,[r16]
680 Load value in register A from the byte pointed to by register r16.
681 Cycles: 2
683 Bytes: 1
685 Flags: None affected.
687 LD A,[n16]
689 Load value in register A from the byte at address n16.
690 Cycles: 4
692 Bytes: 3
694 Flags: None affected.
696 LDH A,[n16]
698 Load value in register A from the byte at address n16, provided the ad‐
699 dress is between $FF00 and $FFFF.
700 Cycles: 3
702 Bytes: 2
704 Flags: None affected.
706 This is sometimes written as ‘LDIO A,[n16]’, or ‘LD A,[$FF00+n8]’.
708 LDH A,[C]
710 Load value in register A from the byte at address $FF00+c.
711 Cycles: 2
713 Bytes: 1
715 Flags: None affected.
717 This is sometimes written as ‘LDIO A,[C]’, or ‘LD A,[$FF00+C]’.
719 LD [HLI],A
721 Store value in register A into the byte pointed by HL and increment HL
722 afterwards.
723 Cycles: 2
725 Bytes: 1
727 Flags: None affected.
729 This is sometimes written as ‘LD [HL+],A’, or ‘LDI [HL],A’.
731 LD [HLD],A
733 Store value in register A into the byte pointed by HL and decrement HL
734 afterwards.
735 Cycles: 2
737 Bytes: 1
739 Flags: None affected.
741 This is sometimes written as ‘LD [HL-],A’, or ‘LDD [HL],A’.
743 LD A,[HLD]
745 Load value into register A from the byte pointed by HL and decrement HL
746 afterwards.
747 Cycles: 2
749 Bytes: 1
751 Flags: None affected.
753 This is sometimes written as ‘LD A,[HL-]’, or ‘LDD A,[HL]’.
755 LD A,[HLI]
757 Load value into register A from the byte pointed by HL and increment HL
758 afterwards.
759 Cycles: 2
761 Bytes: 1
763 Flags: None affected.
765 This is sometimes written as ‘LD A,[HL+]’, or ‘LDI A,[HL]’.
767 LD SP,n16
769 Load value n16 into register SP.
770 Cycles: 3
772 Bytes: 3
774 Flags: None affected.
776 LD [n16],SP
778 Store SP & $FF at address n16 and SP >> 8 at address n16 + 1.
779 Cycles: 5
781 Bytes: 3
783 Flags: None affected.
785 LD HL,SP+e8
787 Add the signed value e8 to SP and store the result in HL.
788 Cycles: 3
790 Bytes: 2
792 Flags:
794 Z 0
795 N 0
796 H Set if overflow from bit 3.
797 C Set if overflow from bit 7.
798 LD SP,HL
800 Load register HL into register SP.
801 Cycles: 2
803 Bytes: 1
805 Flags: None affected.
807 NOP
809 No OPeration.
810 Cycles: 1
812 Bytes: 1
814 Flags: None affected.
816 OR A,r8
818 Store into A the bitwise OR of the value in r8 and A.
819 Cycles: 1
821 Bytes: 1
823 Flags:
825 Z Set if result is 0.
826 N 0
827 H 0
828 C 0
829 OR A,[HL]
831 Store into A the bitwise OR of the byte pointed to by HL and A.
832 Cycles: 2
834 Bytes: 1
836 Flags: See OR A,r8
838 OR A,n8
840 Store into A the bitwise OR of n8 and A.
841 Cycles: 2
843 Bytes: 2
845 Flags: See OR A,r8
847 POP AF
849 Pop register AF from the stack. This is roughly equivalent to the fol‐
850 lowing imaginary instructions:
851 ld f, [sp] ; See below for individual flags
853 inc sp
854 ld a, [sp]
855 inc sp
856 Cycles: 3
858 Bytes: 1
860 Flags:
862 Z Set from bit 7 of the popped low byte.
863 N Set from bit 6 of the popped low byte.
864 H Set from bit 5 of the popped low byte.
865 C Set from bit 4 of the popped low byte.
866 POP r16
868 Pop register r16 from the stack. This is roughly equivalent to the fol‐
869 lowing imaginary instructions:
870 ld LOW(r16), [sp] ; C, E or L
872 inc sp
873 ld HIGH(r16), [sp] ; B, D or H
874 inc sp
875 Cycles: 3
877 Bytes: 1
879 Flags: None affected.
881 PUSH AF
883 Push register AF into the stack. This is roughly equivalent to the fol‐
884 lowing imaginary instructions:
885 dec sp
887 ld [sp], a
888 dec sp
889 ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4
890 Cycles: 4
892 Bytes: 1
894 Flags: None affected.
896 PUSH r16
898 Push register r16 into the stack. This is roughly equivalent to the fol‐
899 lowing imaginary instructions:
900 dec sp
902 ld [sp], HIGH(r16) ; B, D or H
903 dec sp
904 ld [sp], LOW(r16) ; C, E or L
905 Cycles: 4
907 Bytes: 1
909 Flags: None affected.
911 RES u3,r8
913 Set bit u3 in register r8 to 0. Bit 0 is the rightmost one, bit 7 the
914 leftmost one.
915 Cycles: 2
917 Bytes: 2
919 Flags: None affected.
921 RES u3,[HL]
923 Set bit u3 in the byte pointed by HL to 0. Bit 0 is the rightmost one,
924 bit 7 the leftmost one.
925 Cycles: 4
927 Bytes: 2
929 Flags: None affected.
931 RET
933 Return from subroutine. This is basically a POP PC (if such an instruc‐
934 tion existed). See POP r16 for an explanation of how POP works.
935 Cycles: 4
937 Bytes: 1
939 Flags: None affected.
941 RET cc
943 Return from subroutine if condition cc is met.
944 Cycles: 5 taken / 2 untaken
946 Bytes: 1
948 Flags: None affected.
950 RETI
952 Return from subroutine and enable interrupts. This is basically equiva‐
953 lent to executing EI then RET, meaning that IME is set right after this
954 instruction.
955 Cycles: 4
957 Bytes: 1
959 Flags: None affected.
961 RL r8
963 Rotate bits in register r8 left through carry.
964 C <- [7 <- 0] <- C
966 Cycles: 2
968 Bytes: 2
970 Flags:
972 Z Set if result is 0.
973 N 0
974 H 0
975 C Set according to result.
976 RL [HL]
978 Rotate the byte pointed to by HL left through carry.
979 C <- [7 <- 0] <- C
981 Cycles: 4
983 Bytes: 2
985 Flags: See RL r8
987 RLA
989 Rotate register A left through carry.
990 C <- [7 <- 0] <- C
992 Cycles: 1
994 Bytes: 1
996 Flags:
998 Z 0
999 N 0
1000 H 0
1001 C Set according to result.
1002 RLC r8
1004 Rotate register r8 left.
1005 C <- [7 <- 0] <- [7]
1007 Cycles: 2
1009 Bytes: 2
1011 Flags:
1013 Z Set if result is 0.
1014 N 0
1015 H 0
1016 C Set according to result.
1017 RLC [HL]
1019 Rotate the byte pointed to by HL left.
1020 C <- [7 <- 0] <- [7]
1022 Cycles: 4
1024 Bytes: 2
1026 Flags: See RLC r8
1028 RLCA
1030 Rotate register A left.
1031 C <- [7 <- 0] <- [7]
1033 Cycles: 1
1035 Bytes: 1
1037 Flags:
1039 Z 0
1040 N 0
1041 H 0
1042 C Set according to result.
1043 RR r8
1045 Rotate register r8 right through carry.
1046 C -> [7 -> 0] -> C
1048 Cycles: 2
1050 Bytes: 2
1052 Flags:
1054 Z Set if result is 0.
1055 N 0
1056 H 0
1057 C Set according to result.
1058 RR [HL]
1060 Rotate the byte pointed to by HL right through carry.
1061 C -> [7 -> 0] -> C
1063 Cycles: 4
1065 Bytes: 2
1067 Flags: See RR r8
1069 RRA
1071 Rotate register A right through carry.
1072 C -> [7 -> 0] -> C
1074 Cycles: 1
1076 Bytes: 1
1078 Flags:
1080 Z 0
1081 N 0
1082 H 0
1083 C Set according to result.
1084 RRC r8
1086 Rotate register r8 right.
1087 [0] -> [7 -> 0] -> C
1089 Cycles: 2
1091 Bytes: 2
1093 Flags:
1095 Z Set if result is 0.
1096 N 0
1097 H 0
1098 C Set according to result.
1099 RRC [HL]
1101 Rotate the byte pointed to by HL right.
1102 [0] -> [7 -> 0] -> C
1104 Cycles: 4
1106 Bytes: 2
1108 Flags: See RRC r8
1110 RRCA
1112 Rotate register A right.
1113 [0] -> [7 -> 0] -> C
1115 Cycles: 1
1117 Bytes: 1
1119 Flags:
1121 Z 0
1122 N 0
1123 H 0
1124 C Set according to result.
1125 RST vec
1127 Call address vec. This is a shorter and faster equivalent to CALL for
1128 suitable values of vec.
1129 Cycles: 4
1131 Bytes: 1
1133 Flags: None affected.
1135 SBC A,r8
1137 Subtract the value in r8 and the carry flag from A.
1138 Cycles: 1
1140 Bytes: 1
1142 Flags:
1144 Z Set if result is 0.
1145 N 1
1146 H Set if borrow from bit 4.
1147 C Set if borrow (i.e. if (r8 + carry) > A).
1148 SBC A,[HL]
1150 Subtract the byte pointed to by HL and the carry flag from A.
1151 Cycles: 2
1153 Bytes: 1
1155 Flags: See SBC A,r8
1157 SBC A,n8
1159 Subtract the value n8 and the carry flag from A.
1160 Cycles: 2
1162 Bytes: 2
1164 Flags: See SBC A,r8
1166 SCF
1168 Set Carry Flag.
1169 Cycles: 1
1171 Bytes: 1
1173 Flags:
1175 N 0
1176 H 0
1177 C 1
1178 SET u3,r8
1180 Set bit u3 in register r8 to 1. Bit 0 is the rightmost one, bit 7 the
1181 leftmost one.
1182 Cycles: 2
1184 Bytes: 2
1186 Flags: None affected.
1188 SET u3,[HL]
1190 Set bit u3 in the byte pointed by HL to 1. Bit 0 is the rightmost one,
1191 bit 7 the leftmost one.
1192 Cycles: 4
1194 Bytes: 2
1196 Flags: None affected.
1198 SLA r8
1200 Shift Left Arithmetically register r8.
1201 C <- [7 <- 0] <- 0
1203 Cycles: 2
1205 Bytes: 2
1207 Flags:
1209 Z Set if result is 0.
1210 N 0
1211 H 0
1212 C Set according to result.
1213 SLA [HL]
1215 Shift Left Arithmetically the byte pointed to by HL.
1216 C <- [7 <- 0] <- 0
1218 Cycles: 4
1220 Bytes: 2
1222 Flags: See SLA r8
1224 SRA r8
1226 Shift Right Arithmetically register r8.
1227 [7] -> [7 -> 0] -> C
1229 Cycles: 2
1231 Bytes: 2
1233 Flags:
1235 Z Set if result is 0.
1236 N 0
1237 H 0
1238 C Set according to result.
1239 SRA [HL]
1241 Shift Right Arithmetically the byte pointed to by HL.
1242 [7] -> [7 -> 0] -> C
1244 Cycles: 4
1246 Bytes: 2
1248 Flags: See SRA r8
1250 SRL r8
1252 Shift Right Logically register r8.
1253 0 -> [7 -> 0] -> C
1255 Cycles: 2
1257 Bytes: 2
1259 Flags:
1261 Z Set if result is 0.
1262 N 0
1263 H 0
1264 C Set according to result.
1265 SRL [HL]
1267 Shift Right Logically the byte pointed to by HL.
1268 0 -> [7 -> 0] -> C
1270 Cycles: 4
1272 Bytes: 2
1274 Flags: See SRA r8
1276 STOP
1278 Enter CPU very low power mode. Also used to switch between double and
1279 normal speed CPU modes in GBC.
1280 Cycles: -
1282 Bytes: 2
1284 Flags: None affected.
1286 SUB A,r8
1288 Subtract the value in r8 from A.
1289 Cycles: 1
1291 Bytes: 1
1293 Flags:
1295 Z Set if result is 0.
1296 N 1
1297 H Set if borrow from bit 4.
1298 C Set if borrow (set if r8 > A).
1299 SUB A,[HL]
1301 Subtract the byte pointed to by HL from A.
1302 Cycles: 2
1304 Bytes: 1
1306 Flags: See SUB A,r8
1308 SUB A,n8
1310 Subtract the value n8 from A.
1311 Cycles: 2
1313 Bytes: 2
1315 Flags: See SUB A,r8
1317 SWAP r8
1319 Swap the upper 4 bits in register r8 and the lower 4 ones.
1320 Cycles: 2
1322 Bytes: 2
1324 Flags:
1326 Z Set if result is 0.
1327 N 0
1328 H 0
1329 C 0
1330 SWAP [HL]
1332 Swap the upper 4 bits in the byte pointed by HL and the lower 4 ones.
1333 Cycles: 4
1335 Bytes: 2
1337 Flags: See SWAP r8
1339 XOR A,r8
1341 Bitwise XOR between the value in r8 and A.
1342 Cycles: 1
1344 Bytes: 1
1346 Flags:
1348 Z Set if result is 0.
1349 N 0
1350 H 0
1351 C 0
1352 XOR A,[HL]
1354 Bitwise XOR between the byte pointed to by HL and A.
1355 Cycles: 2
1357 Bytes: 1
1359 Flags: See XOR A,r8
1361 XOR A,n8
1363 Bitwise XOR between the value in n8 and A.
1364 Cycles: 2
1366 Bytes: 2
1368 Flags: See XOR A,r8
1370
1372 rgbasm(1), rgbds(7)
1373
1375 rgbds was originally written by Carsten Sørensen as part of the ASMotor
1376 package, and was later packaged in RGBDS by Justin Lloyd. It is now
1377 maintained by a number of contributors at https://github.com/gbdev/rgbds
1378BSD March 28, 2021 BSD