perf-list(1)

1PERF-LIST(1)                      perf Manual                     PERF-LIST(1)
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NAME

6       perf-list - List all symbolic event types
7

SYNOPSIS

9       perf list [--no-desc] [--long-desc]
10                   [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
11

DESCRIPTION

13       This command displays the symbolic event types which can be selected in
14       the various perf commands with the -e option.
15

OPTIONS

17       -d, --desc
18           Print extra event descriptions. (default)
19
20       --no-desc
21           Don’t print descriptions.
22
23       -v, --long-desc
24           Print longer event descriptions.
25
26       --debug
27           Enable debugging output.
28
29       --details
30           Print how named events are resolved internally into perf events,
31           and also any extra expressions computed by perf stat.
32

EVENT MODIFIERS

34       Events can optionally have a modifier by appending a colon and one or
35       more modifiers. Modifiers allow the user to restrict the events to be
36       counted. The following modifiers exist:
37
38           u - user-space counting
39           k - kernel counting
40           h - hypervisor counting
41           I - non idle counting
42           G - guest counting (in KVM guests)
43           H - host counting (not in KVM guests)
44           p - precise level
45           P - use maximum detected precise level
46           S - read sample value (PERF_SAMPLE_READ)
47           D - pin the event to the PMU
48           W - group is weak and will fallback to non-group if not schedulable,
49
50       The p modifier can be used for specifying how precise the instruction
51       address should be. The p modifier can be specified multiple times:
52
53           0 - SAMPLE_IP can have arbitrary skid
54           1 - SAMPLE_IP must have constant skid
55           2 - SAMPLE_IP requested to have 0 skid
56           3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
57               sample shadowing effects.
58
59       For Intel systems precise event sampling is implemented with PEBS which
60       supports up to precise-level 2, and precise level 3 for some special
61       cases
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63       On AMD systems it is implemented using IBS (up to precise-level 2). The
64       precise modifier works with event types 0x76 (cpu-cycles, CPU clocks
65       not halted) and 0xC1 (micro-ops retired). Both events map to IBS
66       execution sampling (IBS op) with the IBS Op Counter Control bit
67       (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
68       Manual Volume 2: System Programming, 13.3 Instruction-Based Sampling).
69       Examples to use IBS:
70
71           perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
72           perf record -a -e r076:p ...          # same as -e cpu-cycles:p
73           perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR

76       Even when an event is not available in a symbolic form within perf
77       right now, it can be encoded in a per processor specific way.
78
79       For instance For x86 CPUs NNN represents the raw register encoding with
80       the layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32
81       Architectures Software Developer’s Manual Volume 3B: System Programming
82       Guide] Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMD’s
83       PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2:
84       System Programming], Page 344, Figure 13-7 Performance Event-Select
85       Register (PerfEvtSeln)).
86
87       Note: Only the following bit fields can be set in x86 counter
88       registers: event, umask, edge, inv, cmask. Esp. guest/host only and
89       OS/user mode flags must be setup using EVENT MODIFIERS.
90
91       Example:
92
93       If the Intel docs for a QM720 Core i7 describe an event as:
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95           Event  Umask  Event Mask
96           Num.   Value  Mnemonic    Description                        Comment
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98           A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
99                                     delivered by loop stream detector  invert to count
100                                                                        cycles
101
102       raw encoding of 0x1A8 can be used:
103
104           perf stat -e r1a8 -a sleep 1
105           perf record -e r1a8 ...
106
107       You should refer to the processor specific documentation for getting
108       these details. Some of them are referenced in the SEE ALSO section
109       below.
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ARBITRARY PMUS

112       perf also supports an extended syntax for specifying raw parameters to
113       PMUs. Using this typically requires looking up the specific event in
114       the CPU vendor specific documentation.
115
116       The available PMUs and their raw parameters can be listed with
117
118           ls /sys/devices/*/format
119
120       For example the raw event "LSD.UOPS" core pmu event above could be
121       specified as
122
123           perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
124
125           or using extended name syntax
126
127           perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
128

PER SOCKET PMUS

130       Some PMUs are not associated with a core, but with a whole CPU socket.
131       Events on these PMUs generally cannot be sampled, but only counted
132       globally with perf stat -a. They can be bound to one logical CPU, but
133       will measure all the CPUs in the same socket.
134
135       This example measures memory bandwidth every second on the first memory
136       controller on socket 0 of a Intel Xeon system
137
138           perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
139
140       Each memory controller has its own PMU. Measuring the complete system
141       bandwidth would require specifying all imc PMUs (see perf list output),
142       and adding the values together. To simplify creation of multiple
143       events, prefix and glob matching is supported in the PMU name, and the
144       prefix uncore_ is also ignored when performing the match. So the
145       command above can be expanded to all memory controllers by using the
146       syntaxes:
147
148           perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
149           perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
150
151       This example measures the combined core power every second
152
153           perf stat -I 1000 -e power/energy-cores/  -a
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ACCESS RESTRICTIONS

156       For non root users generally only context switched PMU events are
157       available. This is normally only the events in the cpu PMU, the
158       predefined events like cycles and instructions and some software
159       events.
160
161       Other PMUs and global measurements are normally root only. Some event
162       qualifiers, such as "any", are also root only.
163
164       This can be overridden by setting the kernel.perf_event_paranoid sysctl
165       to -1, which allows non root to use these events.
166
167       For accessing trace point events perf needs to have read access to
168       /sys/kernel/debug/tracing, even when perf_event_paranoid is in a
169       relaxed setting.
170

TRACING

172       Some PMUs control advanced hardware tracing capabilities, such as Intel
173       PT, that allows low overhead execution tracing. These are described in
174       a separate intel-pt.txt document.
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PARAMETERIZED EVENTS

177       Some pmu events listed by perf-list will be displayed with ? in them.
178       For example:
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180           hv_gpci/dtbp_ptitc,phys_processor_idx=?/
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182       This means that when provided as an event, a value for ? must also be
183       supplied. For example:
184
185           perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
186
187       EVENT QUALIFIERS:
188
189       It is also possible to add extra qualifiers to an event:
190
191       percore:
192
193       Sums up the event counts for all hardware threads in a core, e.g.:
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195           perf stat -e cpu/event=0,umask=0x3,percore=1/
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EVENT GROUPS

198       Perf supports time based multiplexing of events, when the number of
199       events active exceeds the number of hardware performance counters.
200       Multiplexing can cause measurement errors when the workload changes its
201       execution profile.
202
203       When metrics are computed using formulas from event counts, it is
204       useful to ensure some events are always measured together as a group to
205       minimize multiplexing errors. Event groups can be specified using { }.
206
207           perf stat -e '{instructions,cycles}' ...
208
209       The number of available performance counters depend on the CPU. A group
210       cannot contain more events than available counters. For example Intel
211       Core CPUs typically have four generic performance counters for the
212       core, plus three fixed counters for instructions, cycles and
213       ref-cycles. Some special events have restrictions on which counter they
214       can schedule, and may not support multiple instances in a single group.
215       When too many events are specified in the group some of them will not
216       be measured.
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218       Globally pinned events can limit the number of counters available for
219       other groups. On x86 systems, the NMI watchdog pins a counter by
220       default. The nmi watchdog can be disabled as root with
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222           echo 0 > /proc/sys/kernel/nmi_watchdog
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224       Events from multiple different PMUs cannot be mixed in a group, with
225       some exceptions for software events.
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LEADER SAMPLING

228       perf also supports group leader sampling using the :S specifier.
229
230           perf record -e '{cycles,instructions}:S' ...
231           perf report --group
232
233       Normally all events in an event group sample, but with :S only the
234       first event (the leader) samples, and it only reads the values of the
235       other events in the group.
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OPTIONS

238       Without options all known events will be listed.
239
240       To limit the list use:
241
242        1. hw or hardware to list hardware events such as cache-misses, etc.
243
244        2. sw or software to list software events such as context switches,
245           etc.
246
247        3. cache or hwcache to list hardware cache events such as
248           L1-dcache-loads, etc.
249
250        4. tracepoint to list all tracepoint events, alternatively use
251           subsys_glob:event_glob to filter by tracepoint subsystems such as
252           sched, block, etc.
253
254        5. pmu to print the kernel supplied PMU events.
255
256        6. sdt to list all Statically Defined Tracepoint events.
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258        7. metric to list metrics
259
260        8. metricgroup to list metricgroups with metrics.
261
262        9. If none of the above is matched, it will apply the supplied glob to
263           all events, printing the ones that match.
264
265       10. As a last resort, it will do a substring search in all event names.
266
267       One or more types can be used at the same time, listing the events for
268       the types specified.
269
270       Support raw format:
271
272        1. --raw-dump, shows the raw-dump of all the events.
273
274        2. --raw-dump [hw|sw|cache|tracepoint|pmu|event_glob], shows the
275           raw-dump of a certain kind of events.
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NOTES

284        1. Intel® 64 and IA-32 Architectures Software Developer’s Manual
285           Volume 3B: System Programming Guide
286           http://www.intel.com/sdm/
287
288        2. AMD64 Architecture Programmer’s Manual Volume 2: System Programming
289           http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf
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293perf                              11/12/2019                      PERF-LIST(1)