1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-<N>] [--gdwarf-sections]
14 [--gdwarf-cie-version=VERSION]
15 [--help] [-I dir] [-J]
16 [-K] [-L] [--listing-lhs-width=NUM]
17 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18 [--listing-cont-lines=NUM] [--keep-locals]
19 [--no-pad-sections]
20 [-o objfile] [-R]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--generate-missing-build-notes=[no|yes]]
28 [--multibyte-handling=[allow|warn|warn-sym-only]]
29 [--target-help] [target-options]
30 [--|files ...]
31
33 Target AArch64 options:
34 [-EB|-EL]
35 [-mabi=ABI]
36 Target Alpha options:
38 [-mcpu]
39 [-mdebug | -no-mdebug]
40 [-replace | -noreplace]
41 [-relax] [-g] [-Gsize]
42 [-F] [-32addr]
43 Target ARC options:
45 [-mcpu=cpu]
46 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
47 [-mcode-density]
48 [-mrelax]
49 [-EB|-EL]
50 Target ARM options:
52 [-mcpu=processor[+extension...]]
53 [-march=architecture[+extension...]]
54 [-mfpu=floating-point-format]
55 [-mfloat-abi=abi]
56 [-meabi=ver]
57 [-mthumb]
58 [-EB|-EL]
59 [-mapcs-32|-mapcs-26|-mapcs-float|
60 -mapcs-reentrant]
61 [-mthumb-interwork] [-k]
62 Target Blackfin options:
64 [-mcpu=processor[-sirevision]]
65 [-mfdpic]
66 [-mno-fdpic]
67 [-mnopic]
68 Target BPF options:
70 [-EL] [-EB]
71 Target CRIS options:
73 [--underscore | --no-underscore]
74 [--pic] [-N]
75 [--emulation=criself | --emulation=crisaout]
76 [--march=v0_v10 | --march=v10 | --march=v32 |
77 --march=common_v10_v32]
78 Target C-SKY options:
80 [-march=arch] [-mcpu=cpu]
81 [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
82 [-fpic] [-pic]
83 [-mljump] [-mno-ljump]
84 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
85 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
86 [-mnolrw ] [-mno-lrw]
87 [-melrw] [-mno-elrw]
88 [-mlaf ] [-mliterals-after-func]
89 [-mno-laf] [-mno-literals-after-func]
90 [-mlabr] [-mliterals-after-br]
91 [-mno-labr] [-mnoliterals-after-br]
92 [-mistack] [-mno-istack]
93 [-mhard-float] [-mmp] [-mcp] [-mcache]
94 [-msecurity] [-mtrust]
95 [-mdsp] [-medsp] [-mvdsp]
96 Target D10V options:
98 [-O]
99 Target D30V options:
101 [-O|-n|-N]
102 Target EPIPHANY options:
104 [-mepiphany|-mepiphany16]
105 Target H8/300 options:
107 [-h-tick-hex]
108 Target i386 options:
110 [--32|--x32|--64] [-n]
111 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
112 Target IA-64 options:
114 [-mconstant-gp|-mauto-pic]
115 [-milp32|-milp64|-mlp64|-mp64]
116 [-mle|mbe]
117 [-mtune=itanium1|-mtune=itanium2]
118 [-munwind-check=warning|-munwind-check=error]
119 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
120 [-x|-xexplicit] [-xauto] [-xdebug]
121 Target IP2K options:
123 [-mip2022|-mip2022ext]
124 Target M32C options:
126 [-m32c|-m16c] [-relax] [-h-tick-hex]
127 Target M32R options:
129 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
130 --W[n]p]
131 Target M680X0 options:
133 [-l] [-m68000|-m68010|-m68020|...]
134 Target M68HC11 options:
136 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
137 [-mshort|-mlong]
138 [-mshort-double|-mlong-double]
139 [--force-long-branches] [--short-branches]
140 [--strict-direct-mode] [--print-insn-syntax]
141 [--print-opcodes] [--generate-example]
142 Target MCORE options:
144 [-jsri2bsr] [-sifilter] [-relax]
145 [-mcpu=[210|340]]
146 Target Meta options:
148 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
149 Target MIPS options:
151 [-nocpp] [-EL] [-EB] [-O[optimization level]]
152 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
153 [-non_shared] [-xgot [-mvxworks-pic]
154 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
155 [-mfp64] [-mgp64] [-mfpxx]
156 [-modd-spreg] [-mno-odd-spreg]
157 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
158 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
159 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
160 [-mips64r3] [-mips64r5] [-mips64r6]
161 [-construct-floats] [-no-construct-floats]
162 [-mignore-branch-isa] [-mno-ignore-branch-isa]
163 [-mnan=encoding]
164 [-trap] [-no-break] [-break] [-no-trap]
165 [-mips16] [-no-mips16]
166 [-mmips16e2] [-mno-mips16e2]
167 [-mmicromips] [-mno-micromips]
168 [-msmartmips] [-mno-smartmips]
169 [-mips3d] [-no-mips3d]
170 [-mdmx] [-no-mdmx]
171 [-mdsp] [-mno-dsp]
172 [-mdspr2] [-mno-dspr2]
173 [-mdspr3] [-mno-dspr3]
174 [-mmsa] [-mno-msa]
175 [-mxpa] [-mno-xpa]
176 [-mmt] [-mno-mt]
177 [-mmcu] [-mno-mcu]
178 [-mcrc] [-mno-crc]
179 [-mginv] [-mno-ginv]
180 [-mloongson-mmi] [-mno-loongson-mmi]
181 [-mloongson-cam] [-mno-loongson-cam]
182 [-mloongson-ext] [-mno-loongson-ext]
183 [-mloongson-ext2] [-mno-loongson-ext2]
184 [-minsn32] [-mno-insn32]
185 [-mfix7000] [-mno-fix7000]
186 [-mfix-rm7000] [-mno-fix-rm7000]
187 [-mfix-vr4120] [-mno-fix-vr4120]
188 [-mfix-vr4130] [-mno-fix-vr4130]
189 [-mfix-r5900] [-mno-fix-r5900]
190 [-mdebug] [-no-mdebug]
191 [-mpdr] [-mno-pdr]
192 Target MMIX options:
194 [--fixed-special-register-names] [--globalize-symbols]
195 [--gnu-syntax] [--relax] [--no-predefined-symbols]
196 [--no-expand] [--no-merge-gregs] [-x]
197 [--linker-allocated-gregs]
198 Target Nios II options:
200 [-relax-all] [-relax-section] [-no-relax]
201 [-EB] [-EL]
202 Target NDS32 options:
204 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
205 [-misa=isa] [-mabi=abi] [-mall-ext]
206 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
207 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
208 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
209 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
210 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
211 [-mb2bb]
212 Target PDP11 options:
214 [-mpic|-mno-pic] [-mall] [-mno-extensions]
215 [-mextension|-mno-extension]
216 [-mcpu] [-mmachine]
217 Target picoJava options:
219 [-mb|-me]
220 Target PowerPC options:
222 [-a32|-a64]
223 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
224 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
225 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
226 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
227 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
228 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
229 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
230 [-mregnames|-mno-regnames]
231 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
232 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
233 [-msolaris|-mno-solaris]
234 [-nops=count]
235 Target PRU options:
237 [-link-relax]
238 [-mnolink-relax]
239 [-mno-warn-regname-label]
240 Target RISC-V options:
242 [-fpic|-fPIC|-fno-pic]
243 [-march=ISA]
244 [-mabi=ABI]
245 [-mlittle-endian|-mbig-endian]
246 Target RL78 options:
248 [-mg10]
249 [-m32bit-doubles|-m64bit-doubles]
250 Target RX options:
252 [-mlittle-endian|-mbig-endian]
253 [-m32bit-doubles|-m64bit-doubles]
254 [-muse-conventional-section-names]
255 [-msmall-data-limit]
256 [-mpid]
257 [-mrelax]
258 [-mint-register=number]
259 [-mgcc-abi|-mrx-abi]
260 Target s390 options:
262 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
263 [-mregnames|-mno-regnames]
264 [-mwarn-areg-zero]
265 Target SCORE options:
267 [-EB][-EL][-FIXDD][-NWARN]
268 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
269 [-march=score7][-march=score3]
270 [-USE_R1][-KPIC][-O0][-G num][-V]
271 Target SPARC options:
273 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
274 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
275 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
276 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
277 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
278 -Asparcvisr|-Asparc5]
279 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
280 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
281 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
282 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
283 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
284 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
285 -bump]
286 [-32|-64]
287 [--enforce-aligned-data][--dcti-couples-detect]
288 Target TIC54X options:
290 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
291 [-merrors-to-file <filename>|-me <filename>]
292 Target TIC6X options:
294 [-march=arch] [-mbig-endian|-mlittle-endian]
295 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
296 [-mpic|-mno-pic]
297 Target TILE-Gx options:
299 [-m32|-m64][-EB][-EL]
300 Target Visium options:
302 [-mtune=arch]
303 Target Xtensa options:
305 [--[no-]text-section-literals] [--[no-]auto-litpools]
306 [--[no-]absolute-literals]
307 [--[no-]target-align] [--[no-]longcalls]
308 [--[no-]transform]
309 [--rename-section oldname=newname]
310 [--[no-]trampolines]
311 [--abi-windowed|--abi-call0]
312 Target Z80 options:
314 [-march=CPU[-EXT][+EXT]]
315 [-local-prefix=PREFIX]
316 [-colonless]
317 [-sdcc]
318 [-fp-s=FORMAT]
319 [-fp-d=FORMAT]
320
322 GNU as is really a family of assemblers. If you use (or have used) the
323 GNU assembler on one architecture, you should find a fairly similar
324 environment when you use it on another architecture. Each version has
325 much in common with the others, including object file formats, most
326 assembler directives (often called pseudo-ops) and assembler syntax.
327 as is primarily intended to assemble the output of the GNU C compiler
329 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
330 assemble correctly everything that other assemblers for the same
331 machine would assemble. Any exceptions are documented explicitly.
332 This doesn't mean as always uses the same syntax as another assembler
333 for the same architecture; for example, we know of several incompatible
334 versions of 680x0 assembly language syntax.
335 Each time you run as it assembles exactly one source program. The
337 source program is made up of one or more files. (The standard input is
338 also a file.)
339 You give as a command line that has zero or more input file names. The
341 input files are read (from left file name to right). A command-line
342 argument (in any position) that has no special meaning is taken to be
343 an input file name.
344 If you give as no file names it attempts to read one input file from
346 the as standard input, which is normally your terminal. You may have
347 to type ctl-D to tell as there is no more program to assemble.
348 Use -- if you need to explicitly name the standard input file in your
350 command line.
351 If the source is empty, as produces a small, empty object file.
353 as may write warnings and error messages to the standard error file
355 (usually your terminal). This should not happen when a compiler runs
356 as automatically. Warnings report an assumption made so that as could
357 keep assembling a flawed program; errors report a grave problem that
358 stops the assembly.
359 If you are invoking as via the GNU C compiler, you can use the -Wa
361 option to pass arguments through to the assembler. The assembler
362 arguments must be separated from each other (and the -Wa) by commas.
363 For example:
364 gcc -c -g -O -Wa,-alh,-L file.c
366 This passes two options to the assembler: -alh (emit a listing to
368 standard output with high-level and assembly source) and -L (retain
369 local symbols in the symbol table).
370 Usually you do not need to use this -Wa mechanism, since many compiler
372 command-line options are automatically passed to the assembler by the
373 compiler. (You can call the GNU compiler driver with the -v option to
374 see precisely what options it passes to each compilation pass,
375 including the assembler.)
376
378 @file
379 Read command-line options from file. The options read are inserted
380 in place of the original @file option. If file does not exist, or
381 cannot be read, then the option will be treated literally, and not
382 removed.
383 Options in file are separated by whitespace. A whitespace
385 character may be included in an option by surrounding the entire
386 option in either single or double quotes. Any character (including
387 a backslash) may be included by prefixing the character to be
388 included with a backslash. The file may itself contain additional
389 @file options; any such options will be processed recursively.
390 -a[cdghlmns]
392 Turn on listings, in any of a variety of ways:
393 -ac omit false conditionals
395 -ad omit debugging directives
397 -ag include general information, like as version and options passed
399 -ah include high-level source
401 -al include assembly
403 -am include macro expansions
405 -an omit forms processing
407 -as include symbols
409 =file
411 set the name of the listing file
412 You may combine these options; for example, use -aln for assembly
414 listing without forms processing. The =file option, if used, must
415 be the last one. By itself, -a defaults to -ahls.
416 --alternate
418 Begin in alternate macro mode.
419 --compress-debug-sections
421 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
422 the ELF ABI. The resulting object file may not be compatible with
423 older linkers and object file utilities. Note if compression would
424 make a given section larger then it is not compressed.
425 --compress-debug-sections=none
427 --compress-debug-sections=zlib
428 --compress-debug-sections=zlib-gnu
429 --compress-debug-sections=zlib-gabi
430 These options control how DWARF debug sections are compressed.
431 --compress-debug-sections=none is equivalent to
432 --nocompress-debug-sections. --compress-debug-sections=zlib and
433 --compress-debug-sections=zlib-gabi are equivalent to
434 --compress-debug-sections. --compress-debug-sections=zlib-gnu
435 compresses DWARF debug sections using zlib. The debug sections are
436 renamed to begin with .zdebug. Note if compression would make a
437 given section larger then it is not compressed nor renamed.
438 --nocompress-debug-sections
440 Do not compress DWARF debug sections. This is usually the default
441 for all targets except the x86/x86_64, but a configure time option
442 can be used to override this.
443 -D Ignored. This option is accepted for script compatibility with
445 calls to other assemblers.
446 --debug-prefix-map old=new
448 When assembling files in directory old, record debugging
449 information describing them as in new instead.
450 --defsym sym=value
452 Define the symbol sym to be value before assembling the input file.
453 value must be an integer constant. As in C, a leading 0x indicates
454 a hexadecimal value, and a leading 0 indicates an octal value. The
455 value of the symbol can be overridden inside a source file via the
456 use of a ".set" pseudo-op.
457 -f "fast"---skip whitespace and comment preprocessing (assume source
459 is compiler output).
460 -g
462 --gen-debug
463 Generate debugging information for each assembler source line using
464 whichever debug format is preferred by the target. This currently
465 means either STABS, ECOFF or DWARF2. When the debug format is
466 DWARF then a ".debug_info" and ".debug_line" section is only
467 emitted when the assembly file doesn't generate one itself.
468 --gstabs
470 Generate stabs debugging information for each assembler line. This
471 may help debugging assembler code, if the debugger can handle it.
472 --gstabs+
474 Generate stabs debugging information for each assembler line, with
475 GNU extensions that probably only gdb can handle, and that could
476 make other debuggers crash or refuse to read your program. This
477 may help debugging assembler code. Currently the only GNU
478 extension is the location of the current working directory at
479 assembling time.
480 --gdwarf-2
482 Generate DWARF2 debugging information for each assembler line.
483 This may help debugging assembler code, if the debugger can handle
484 it. Note---this option is only supported by some targets, not all
485 of them.
486 --gdwarf-3
488 This option is the same as the --gdwarf-2 option, except that it
489 allows for the possibility of the generation of extra debug
490 information as per version 3 of the DWARF specification. Note -
491 enabling this option does not guarantee the generation of any extra
492 information, the choice to do so is on a per target basis.
493 --gdwarf-4
495 This option is the same as the --gdwarf-2 option, except that it
496 allows for the possibility of the generation of extra debug
497 information as per version 4 of the DWARF specification. Note -
498 enabling this option does not guarantee the generation of any extra
499 information, the choice to do so is on a per target basis.
500 --gdwarf-5
502 This option is the same as the --gdwarf-2 option, except that it
503 allows for the possibility of the generation of extra debug
504 information as per version 5 of the DWARF specification. Note -
505 enabling this option does not guarantee the generation of any extra
506 information, the choice to do so is on a per target basis.
507 --gdwarf-sections
509 Instead of creating a .debug_line section, create a series of
510 .debug_line.foo sections where foo is the name of the corresponding
511 code section. For example a code section called .text.func will
512 have its dwarf line number information placed into a section called
513 .debug_line.text.func. If the code section is just called .text
514 then debug line section will still be called just .debug_line
515 without any suffix.
516 --gdwarf-cie-version=version
518 Control which version of DWARF Common Information Entries (CIEs)
519 are produced. When this flag is not specificed the default is
520 version 1, though some targets can modify this default. Other
521 possible values for version are 3 or 4.
522 --size-check=error
524 --size-check=warning
525 Issue an error or warning for invalid ELF .size directive.
526 --elf-stt-common=no
528 --elf-stt-common=yes
529 These options control whether the ELF assembler should generate
530 common symbols with the "STT_COMMON" type. The default can be
531 controlled by a configure option --enable-elf-stt-common.
532 --generate-missing-build-notes=yes
534 --generate-missing-build-notes=no
535 These options control whether the ELF assembler should generate GNU
536 Build attribute notes if none are present in the input sources.
537 The default can be controlled by the --enable-generate-build-notes
538 configure option.
539 --help
541 Print a summary of the command-line options and exit.
542 --target-help
544 Print a summary of all target specific options and exit.
545 -I dir
547 Add directory dir to the search list for ".include" directives.
548 -J Don't warn about signed overflow.
550 -K Issue warnings when difference tables altered for long
552 displacements.
553 -L
555 --keep-locals
556 Keep (in the symbol table) local symbols. These symbols start with
557 system-specific local label prefixes, typically .L for ELF systems
558 or L for traditional a.out systems.
559 --listing-lhs-width=number
561 Set the maximum width, in words, of the output data column for an
562 assembler listing to number.
563 --listing-lhs-width2=number
565 Set the maximum width, in words, of the output data column for
566 continuation lines in an assembler listing to number.
567 --listing-rhs-width=number
569 Set the maximum width of an input source line, as displayed in a
570 listing, to number bytes.
571 --listing-cont-lines=number
573 Set the maximum number of lines printed in a listing for a single
574 line of input to number + 1.
575 --multibyte-handling=allow
577 --multibyte-handling=warn
578 --multibyte-handling=warn-sym-only
579 Controls how the assembler handles multibyte characters in the
580 input. The default (which can be restored by using the allow
581 argument) is to allow such characters without complaint. Using the
582 warn argument will make the assembler generate a warning message
583 whenever any multibyte character is encountered. Using the warn-
584 sym-only argument will only cause a warning to be generated when a
585 symbol is defined with a name that contains multibyte characters.
586 (References to undefined symbols will not generate a warning).
587 --no-pad-sections
589 Stop the assembler for padding the ends of output sections to the
590 alignment of that section. The default is to pad the sections, but
591 this can waste space which might be needed on targets which have
592 tight memory constraints.
593 -o objfile
595 Name the object-file output from as objfile.
596 -R Fold the data section into the text section.
598 --sectname-subst
600 Honor substitution sequences in section names.
601 --statistics
603 Print the maximum space (in bytes) and total time (in seconds) used
604 by assembly.
605 --strip-local-absolute
607 Remove local absolute symbols from the outgoing symbol table.
608 -v
610 -version
611 Print the as version.
612 --version
614 Print the as version and exit.
615 -W
617 --no-warn
618 Suppress warning messages.
619 --fatal-warnings
621 Treat warnings as errors.
622 --warn
624 Don't suppress warning messages or treat them as errors.
625 -w Ignored.
627 -x Ignored.
629 -Z Generate an object file even after errors.
631 -- | files ...
633 Standard input, or source files to assemble.
634 The following options are available when as is configured for the
636 64-bit mode of the ARM Architecture (AArch64).
637 -EB This option specifies that the output generated by the assembler
639 should be marked as being encoded for a big-endian processor.
640 -EL This option specifies that the output generated by the assembler
642 should be marked as being encoded for a little-endian processor.
643 -mabi=abi
645 Specify which ABI the source code uses. The recognized arguments
646 are: "ilp32" and "lp64", which decides the generated object file in
647 ELF32 and ELF64 format respectively. The default is "lp64".
648 -mcpu=processor[+extension...]
650 This option specifies the target processor. The assembler will
651 issue an error message if an attempt is made to assemble an
652 instruction which will not execute on the target processor. The
653 following processor names are recognized: "cortex-a34",
654 "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
655 "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
656 "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77",
657 "cortex-a78", "cortex-a78ae", "cortex-a78c", "ares", "exynos-m1",
658 "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1",
659 "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1"
660 "xgene2", "cortex-r82", and "cortex-x1". The special name "all"
661 may be used to allow the assembler to accept instructions valid for
662 any supported processor, including all optional extensions.
663 In addition to the basic instruction set, the assembler can be told
665 to accept, or restrict, various extension mnemonics that extend the
666 processor.
667 If some implementations of a particular processor can have an
669 extension, then then those extensions are automatically enabled.
670 Consequently, you will not normally have to specify any additional
671 extensions.
672 -march=architecture[+extension...]
674 This option specifies the target architecture. The assembler will
675 issue an error message if an attempt is made to assemble an
676 instruction which will not execute on the target architecture. The
677 following architecture names are recognized: "armv8-a",
678 "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a",
679 "armv8.6-a", "armv8.7-a", and "armv8-r".
680 If both -mcpu and -march are specified, the assembler will use the
682 setting for -mcpu. If neither are specified, the assembler will
683 default to -mcpu=all.
684 The architecture option can be extended with the same instruction
686 set extension options as the -mcpu option. Unlike -mcpu,
687 extensions are not always enabled by default,
688 -mverbose-error
690 This option enables verbose error messages for AArch64 gas. This
691 option is enabled by default.
692 -mno-verbose-error
694 This option disables verbose error messages in AArch64 gas.
695 The following options are available when as is configured for an Alpha
697 processor.
698 -mcpu
700 This option specifies the target processor. If an attempt is made
701 to assemble an instruction which will not execute on the target
702 processor, the assembler may either expand the instruction as a
703 macro or issue an error message. This option is equivalent to the
704 ".arch" directive.
705 The following processor names are recognized: 21064, "21064a",
707 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
708 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
709 "ev67", "ev68". The special name "all" may be used to allow the
710 assembler to accept instructions valid for any Alpha processor.
711 In order to support existing practice in OSF/1 with respect to
713 ".arch", and existing practice within MILO (the Linux ARC
714 bootloader), the numbered processor names (e.g. 21064) enable the
715 processor-specific PALcode instructions, while the "electro-vlasic"
716 names (e.g. "ev4") do not.
717 -mdebug
719 -no-mdebug
720 Enables or disables the generation of ".mdebug" encapsulation for
721 stabs directives and procedure descriptors. The default is to
722 automatically enable ".mdebug" when the first stabs directive is
723 seen.
724 -relax
726 This option forces all relocations to be put into the object file,
727 instead of saving space and resolving some relocations at assembly
728 time. Note that this option does not propagate all symbol
729 arithmetic into the object file, because not all symbol arithmetic
730 can be represented. However, the option can still be useful in
731 specific applications.
732 -replace
734 -noreplace
735 Enables or disables the optimization of procedure calls, both at
736 assemblage and at link time. These options are only available for
737 VMS targets and "-replace" is the default. See section 1.4.1 of
738 the OpenVMS Linker Utility Manual.
739 -g This option is used when the compiler generates debug information.
741 When gcc is using mips-tfile to generate debug information for
742 ECOFF, local labels must be passed through to the object file.
743 Otherwise this option has no effect.
744 -Gsize
746 A local common symbol larger than size is placed in ".bss", while
747 smaller symbols are placed in ".sbss".
748 -F
750 -32addr
751 These options are ignored for backward compatibility.
752 The following options are available when as is configured for an ARC
754 processor.
755 -mcpu=cpu
757 This option selects the core processor variant.
758 -EB | -EL
760 Select either big-endian (-EB) or little-endian (-EL) output.
761 -mcode-density
763 Enable Code Density extension instructions.
764 The following options are available when as is configured for the ARM
766 processor family.
767 -mcpu=processor[+extension...]
769 Specify which ARM processor variant is the target.
770 -march=architecture[+extension...]
772 Specify which ARM architecture variant is used by the target.
773 -mfpu=floating-point-format
775 Select which Floating Point architecture is the target.
776 -mfloat-abi=abi
778 Select which floating point ABI is in use.
779 -mthumb
781 Enable Thumb only instruction decoding.
782 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
784 Select which procedure calling convention is in use.
785 -EB | -EL
787 Select either big-endian (-EB) or little-endian (-EL) output.
788 -mthumb-interwork
790 Specify that the code has been generated with interworking between
791 Thumb and ARM code in mind.
792 -mccs
794 Turns on CodeComposer Studio assembly syntax compatibility mode.
795 -k Specify that PIC code has been generated.
797 The following options are available when as is configured for the
799 Blackfin processor family.
800 -mcpu=processor[-sirevision]
802 This option specifies the target processor. The optional
803 sirevision is not used in assembler. It's here such that GCC can
804 easily pass down its "-mcpu=" option. The assembler will issue an
805 error message if an attempt is made to assemble an instruction
806 which will not execute on the target processor. The following
807 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
808 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
809 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
810 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
811 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
812 "bf549", "bf549m", "bf561", and "bf592".
813 -mfdpic
815 Assemble for the FDPIC ABI.
816 -mno-fdpic
818 -mnopic
819 Disable -mfdpic.
820 The following options are available when as is configured for the Linux
822 kernel BPF processor family.
823 @chapter BPF Dependent Features
825 Options
827 -EB This option specifies that the assembler should emit big-endian
828 eBPF.
829 -EL This option specifies that the assembler should emit little-endian
831 eBPF.
832 Note that if no endianness option is specified in the command line, the
834 host endianness is used. See the info pages for documentation of the
835 CRIS-specific options.
836 The following options are available when as is configured for the C-SKY
838 processor family.
839 -march=archname
841 Assemble for architecture archname. The --help option lists valid
842 values for archname.
843 -mcpu=cpuname
845 Assemble for architecture cpuname. The --help option lists valid
846 values for cpuname.
847 -EL
849 -mlittle-endian
850 Generate little-endian output.
851 -EB
853 -mbig-endian
854 Generate big-endian output.
855 -fpic
857 -pic
858 Generate position-independent code.
859 -mljump
861 -mno-ljump
862 Enable/disable transformation of the short branch instructions
863 "jbf", "jbt", and "jbr" to "jmpi". This option is for V2
864 processors only. It is ignored on CK801 and CK802 targets, which
865 do not support the "jmpi" instruction, and is enabled by default
866 for other processors.
867 -mbranch-stub
869 -mno-branch-stub
870 Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
871 instructions to the linker.
872 This option is only available for bare-metal C-SKY V2 ELF targets,
874 where it is enabled by default. It cannot be used in code that
875 will be dynamically linked against shared libraries.
876 -force2bsr
878 -mforce2bsr
879 -no-force2bsr
880 -mno-force2bsr
881 Enable/disable transformation of "jbsr" instructions to "bsr".
882 This option is always enabled (and -mno-force2bsr is ignored) for
883 CK801/CK802 targets. It is also always enabled when -mbranch-stub
884 is in effect.
885 -jsri2bsr
887 -mjsri2bsr
888 -no-jsri2bsr
889 -mno-jsri2bsr
890 Enable/disable transformation of "jsri" instructions to "bsr".
891 This option is enabled by default.
892 -mnolrw
894 -mno-lrw
895 Enable/disable transformation of "lrw" instructions into a
896 "movih"/"ori" pair.
897 -melrw
899 -mno-elrw
900 Enable/disable extended "lrw" instructions. This option is enabled
901 by default for CK800-series processors.
902 -mlaf
904 -mliterals-after-func
905 -mno-laf
906 -mno-literals-after-func
907 Enable/disable placement of literal pools after each function.
908 -mlabr
910 -mliterals-after-br
911 -mno-labr
912 -mnoliterals-after-br
913 Enable/disable placement of literal pools after unconditional
914 branches. This option is enabled by default.
915 -mistack
917 -mno-istack
918 Enable/disable interrupt stack instructions. This option is
919 enabled by default on CK801, CK802, and CK802 processors.
920 The following options explicitly enable certain optional instructions.
922 These features are also enabled implicitly by using "-mcpu=" to specify
923 a processor that supports it.
924 -mhard-float
926 Enable hard float instructions.
927 -mmp
929 Enable multiprocessor instructions.
930 -mcp
932 Enable coprocessor instructions.
933 -mcache
935 Enable cache prefetch instruction.
936 -msecurity
938 Enable C-SKY security instructions.
939 -mtrust
941 Enable C-SKY trust instructions.
942 -mdsp
944 Enable DSP instructions.
945 -medsp
947 Enable enhanced DSP instructions.
948 -mvdsp
950 Enable vector DSP instructions.
951 The following options are available when as is configured for an
953 Epiphany processor.
954 -mepiphany
956 Specifies that the both 32 and 16 bit instructions are allowed.
957 This is the default behavior.
958 -mepiphany16
960 Restricts the permitted instructions to just the 16 bit set.
961 The following options are available when as is configured for an H8/300
963 processor. @chapter H8/300 Dependent Features
964 Options
966 The Renesas H8/300 version of "as" has one machine-dependent option:
967 -h-tick-hex
969 Support H'00 style hex constants in addition to 0x00 style.
970 -mach=name
972 Sets the H8300 machine variant. The following machine names are
973 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
974 "h8300sxn".
975 The following options are available when as is configured for an i386
977 processor.
978 --32 | --x32 | --64
980 Select the word size, either 32 bits or 64 bits. --32 implies
981 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
982 architecture with 32-bit or 64-bit word-size respectively.
983 These options are only available with the ELF object file format,
985 and require that the necessary BFD support has been included (on a
986 32-bit platform you have to add --enable-64-bit-bfd to configure
987 enable 64-bit usage and use x86-64 as target platform).
988 -n By default, x86 GAS replaces multiple nop instructions used for
990 alignment within code sections with multi-byte nop instructions
991 such as leal 0(%esi,1),%esi. This switch disables the optimization
992 if a single byte nop (0x90) is explicitly specified as the fill
993 byte for alignment.
994 --divide
996 On SVR4-derived platforms, the character / is treated as a comment
997 character, which means that it cannot be used in expressions. The
998 --divide option turns / into a normal character. This does not
999 disable / at the beginning of a line starting a comment, or affect
1000 using # for starting a comment.
1001 -march=CPU[+EXTENSION...]
1003 This option specifies the target processor. The assembler will
1004 issue an error message if an attempt is made to assemble an
1005 instruction which will not execute on the target processor. The
1006 following processor names are recognized: "i8086", "i186", "i286",
1007 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
1008 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
1009 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
1010 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
1011 "bdver3", "bdver4", "znver1", "znver2", "znver3", "btver1",
1012 "btver2", "generic32" and "generic64".
1013 In addition to the basic instruction set, the assembler can be told
1015 to accept various extension mnemonics. For example,
1016 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
1017 following extensions are currently supported: 8087, 287, 387, 687,
1018 "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1019 "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1020 "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nosse4a",
1021 "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2",
1022 "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
1023 "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq",
1024 "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b",
1025 "enqcmd", "serialize", "tsxldtrk", "kl", "nokl", "widekl",
1026 "nowidekl", "hreset", "avx512f", "avx512cd", "avx512er",
1027 "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma",
1028 "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
1029 "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1030 "avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni",
1031 "noavx512f", "noavx512cd", "noavx512er", "noavx512pf",
1032 "noavx512vl", "noavx512bw", "noavx512dq", "noavx512ifma",
1033 "noavx512vbmi", "noavx512_4fmaps", "noavx512_4vnniw",
1034 "noavx512_vpopcntdq", "noavx512_vbmi2", "noavx512_vnni",
1035 "noavx512_bitalg", "noavx512_vp2intersect", "notdx",
1036 "noavx512_bf16", "noavx_vnni", "noenqcmd", "noserialize",
1037 "notsxldtrk", "amx_int8", "noamx_int8", "amx_bf16", "noamx_bf16",
1038 "amx_tile", "noamx_tile", "nouintr", "nohreset", "vmx", "vmfunc",
1039 "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul",
1040 "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept",
1041 "lzcnt", "popcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx",
1042 "clzero", "wbnoinvd", "pconfig", "waitpkg", "uintr", "cldemote",
1043 "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop", "cx16",
1044 "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "snp",
1045 "invlpgb", "tlbsync", "svme" and "padlock". Note that rather than
1046 extending a basic instruction set, the extension mnemonics starting
1047 with "no" revoke the respective functionality.
1048 When the ".arch" directive is used with -march, the ".arch"
1050 directive will take precedent.
1051 -mtune=CPU
1053 This option specifies a processor to optimize for. When used in
1054 conjunction with the -march option, only instructions of the
1055 processor specified by the -march option will be generated.
1056 Valid CPU values are identical to the processor list of -march=CPU.
1058 -msse2avx
1060 This option specifies that the assembler should encode SSE
1061 instructions with VEX prefix.
1062 -msse-check=none
1064 -msse-check=warning
1065 -msse-check=error
1066 These options control if the assembler should check SSE
1067 instructions. -msse-check=none will make the assembler not to
1068 check SSE instructions, which is the default. -msse-check=warning
1069 will make the assembler issue a warning for any SSE instruction.
1070 -msse-check=error will make the assembler issue an error for any
1071 SSE instruction.
1072 -mavxscalar=128
1074 -mavxscalar=256
1075 These options control how the assembler should encode scalar AVX
1076 instructions. -mavxscalar=128 will encode scalar AVX instructions
1077 with 128bit vector length, which is the default. -mavxscalar=256
1078 will encode scalar AVX instructions with 256bit vector length.
1079 WARNING: Don't use this for production code - due to CPU errata the
1081 resulting code may not work on certain models.
1082 -mvexwig=0
1084 -mvexwig=1
1085 These options control how the assembler should encode VEX.W-ignored
1086 (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX
1087 instructions with vex.w = 0, which is the default. -mvexwig=1 will
1088 encode WIG EVEX instructions with vex.w = 1.
1089 WARNING: Don't use this for production code - due to CPU errata the
1091 resulting code may not work on certain models.
1092 -mevexlig=128
1094 -mevexlig=256
1095 -mevexlig=512
1096 These options control how the assembler should encode length-
1097 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
1098 EVEX instructions with 128bit vector length, which is the default.
1099 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1100 with 256bit and 512bit vector length, respectively.
1101 -mevexwig=0
1103 -mevexwig=1
1104 These options control how the assembler should encode w-ignored
1105 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
1106 instructions with evex.w = 0, which is the default. -mevexwig=1
1107 will encode WIG EVEX instructions with evex.w = 1.
1108 -mmnemonic=att
1110 -mmnemonic=intel
1111 This option specifies instruction mnemonic for matching
1112 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
1113 will take precedent.
1114 -msyntax=att
1116 -msyntax=intel
1117 This option specifies instruction syntax when processing
1118 instructions. The ".att_syntax" and ".intel_syntax" directives
1119 will take precedent.
1120 -mnaked-reg
1122 This option specifies that registers don't require a % prefix. The
1123 ".att_syntax" and ".intel_syntax" directives will take precedent.
1124 -madd-bnd-prefix
1126 This option forces the assembler to add BND prefix to all branches,
1127 even if such prefix was not explicitly specified in the source
1128 code.
1129 -mno-shared
1131 On ELF target, the assembler normally optimizes out non-PLT
1132 relocations against defined non-weak global branch targets with
1133 default visibility. The -mshared option tells the assembler to
1134 generate code which may go into a shared library where all non-weak
1135 global branch targets with default visibility can be preempted.
1136 The resulting code is slightly bigger. This option only affects
1137 the handling of branch instructions.
1138 -mbig-obj
1140 On PE/COFF target this option forces the use of big object file
1141 format, which allows more than 32768 sections.
1142 -momit-lock-prefix=no
1144 -momit-lock-prefix=yes
1145 These options control how the assembler should encode lock prefix.
1146 This option is intended as a workaround for processors, that fail
1147 on lock prefix. This option can only be safely used with single-
1148 core, single-thread computers -momit-lock-prefix=yes will omit all
1149 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
1150 usual, which is the default.
1151 -mfence-as-lock-add=no
1153 -mfence-as-lock-add=yes
1154 These options control how the assembler should encode lfence,
1155 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
1156 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1157 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
1158 encode lfence, mfence and sfence as usual, which is the default.
1159 -mrelax-relocations=no
1161 -mrelax-relocations=yes
1162 These options control whether the assembler should generate relax
1163 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1164 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1165 -mrelax-relocations=yes will generate relax relocations.
1166 -mrelax-relocations=no will not generate relax relocations. The
1167 default can be controlled by a configure option
1168 --enable-x86-relax-relocations.
1169 -malign-branch-boundary=NUM
1171 This option controls how the assembler should align branches with
1172 segment prefixes or NOP. NUM must be a power of 2. It should be 0
1173 or no less than 16. Branches will be aligned within NUM byte
1174 boundary. -malign-branch-boundary=0, which is the default, doesn't
1175 align branches.
1176 -malign-branch=TYPE[+TYPE...]
1178 This option specifies types of branches to align. TYPE is
1179 combination of jcc, which aligns conditional jumps, fused, which
1180 aligns fused conditional jumps, jmp, which aligns unconditional
1181 jumps, call which aligns calls, ret, which aligns rets, indirect,
1182 which aligns indirect jumps and calls. The default is
1183 -malign-branch=jcc+fused+jmp.
1184 -malign-branch-prefix-size=NUM
1186 This option specifies the maximum number of prefixes on an
1187 instruction to align branches. NUM should be between 0 and 5. The
1188 default NUM is 5.
1189 -mbranches-within-32B-boundaries
1191 This option aligns conditional jumps, fused conditional jumps and
1192 unconditional jumps within 32 byte boundary with up to 5 segment
1193 prefixes on an instruction. It is equivalent to
1194 -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1195 -malign-branch-prefix-size=5. The default doesn't align branches.
1196 -mlfence-after-load=no
1198 -mlfence-after-load=yes
1199 These options control whether the assembler should generate lfence
1200 after load instructions. -mlfence-after-load=yes will generate
1201 lfence. -mlfence-after-load=no will not generate lfence, which is
1202 the default.
1203 -mlfence-before-indirect-branch=none
1205 -mlfence-before-indirect-branch=all
1206 -mlfence-before-indirect-branch=register
1207 -mlfence-before-indirect-branch=memory
1208 These options control whether the assembler should generate lfence
1209 before indirect near branch instructions.
1210 -mlfence-before-indirect-branch=all will generate lfence before
1211 indirect near branch via register and issue a warning before
1212 indirect near branch via memory. It also implicitly sets
1213 -mlfence-before-ret=shl when there's no explicit
1214 -mlfence-before-ret=. -mlfence-before-indirect-branch=register
1215 will generate lfence before indirect near branch via register.
1216 -mlfence-before-indirect-branch=memory will issue a warning before
1217 indirect near branch via memory.
1218 -mlfence-before-indirect-branch=none will not generate lfence nor
1219 issue warning, which is the default. Note that lfence won't be
1220 generated before indirect near branch via register with
1221 -mlfence-after-load=yes since lfence will be generated after
1222 loading branch target register.
1223 -mlfence-before-ret=none
1225 -mlfence-before-ret=shl
1226 -mlfence-before-ret=or
1227 -mlfence-before-ret=yes
1228 -mlfence-before-ret=not
1229 These options control whether the assembler should generate lfence
1230 before ret. -mlfence-before-ret=or will generate generate or
1231 instruction with lfence. -mlfence-before-ret=shl/yes will generate
1232 shl instruction with lfence. -mlfence-before-ret=not will generate
1233 not instruction with lfence. -mlfence-before-ret=none will not
1234 generate lfence, which is the default.
1235 -mx86-used-note=no
1237 -mx86-used-note=yes
1238 These options control whether the assembler should generate
1239 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1240 property notes. The default can be controlled by the
1241 --enable-x86-used-note configure option.
1242 -mevexrcig=rne
1244 -mevexrcig=rd
1245 -mevexrcig=ru
1246 -mevexrcig=rz
1247 These options control how the assembler should encode SAE-only EVEX
1248 instructions. -mevexrcig=rne will encode RC bits of EVEX
1249 instruction with 00, which is the default. -mevexrcig=rd,
1250 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1251 instructions with 01, 10 and 11 RC bits, respectively.
1252 -mamd64
1254 -mintel64
1255 This option specifies that the assembler should accept only AMD64
1256 or Intel64 ISA in 64-bit mode. The default is to accept common,
1257 Intel64 only and AMD64 ISAs.
1258 -O0 | -O | -O1 | -O2 | -Os
1260 Optimize instruction encoding with smaller instruction size. -O
1261 and -O1 encode 64-bit register load instructions with 64-bit
1262 immediate as 32-bit register load instructions with 31-bit or
1263 32-bits immediates, encode 64-bit register clearing instructions
1264 with 32-bit register clearing instructions, encode 256-bit/512-bit
1265 VEX/EVEX vector register clearing instructions with 128-bit VEX
1266 vector register clearing instructions, encode 128-bit/256-bit EVEX
1267 vector register load/store instructions with VEX vector register
1268 load/store instructions, and encode 128-bit/256-bit EVEX packed
1269 integer logical instructions with 128-bit/256-bit VEX packed
1270 integer logical.
1271 -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1273 vector register clearing instructions with 128-bit EVEX vector
1274 register clearing instructions. In 64-bit mode VEX encoded
1275 instructions with commutative source operands will also have their
1276 source operands swapped if this allows using the 2-byte VEX prefix
1277 form instead of the 3-byte one. Certain forms of AND as well as OR
1278 with the same (register) operand specified twice will also be
1279 changed to TEST.
1280 -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1282 64-bit register tests with immediate as 8-bit register test with
1283 immediate. -O0 turns off this optimization.
1284 The following options are available when as is configured for the
1286 Ubicom IP2K series.
1287 -mip2022ext
1289 Specifies that the extended IP2022 instructions are allowed.
1290 -mip2022
1292 Restores the default behaviour, which restricts the permitted
1293 instructions to just the basic IP2022 ones.
1294 The following options are available when as is configured for the
1296 Renesas M32C and M16C processors.
1297 -m32c
1299 Assemble M32C instructions.
1300 -m16c
1302 Assemble M16C instructions (the default).
1303 -relax
1305 Enable support for link-time relaxations.
1306 -h-tick-hex
1308 Support H'00 style hex constants in addition to 0x00 style.
1309 The following options are available when as is configured for the
1311 Renesas M32R (formerly Mitsubishi M32R) series.
1312 --m32rx
1314 Specify which processor in the M32R family is the target. The
1315 default is normally the M32R, but this option changes it to the
1316 M32RX.
1317 --warn-explicit-parallel-conflicts or --Wp
1319 Produce warning messages when questionable parallel constructs are
1320 encountered.
1321 --no-warn-explicit-parallel-conflicts or --Wnp
1323 Do not produce warning messages when questionable parallel
1324 constructs are encountered.
1325 The following options are available when as is configured for the
1327 Motorola 68000 series.
1328 -l Shorten references to undefined symbols, to one word instead of
1330 two.
1331 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1333 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1334 | -m68333 | -m68340 | -mcpu32 | -m5200
1335 Specify what processor in the 68000 family is the target. The
1336 default is normally the 68020, but this can be changed at
1337 configuration time.
1338 -m68881 | -m68882 | -mno-68881 | -mno-68882
1340 The target machine does (or does not) have a floating-point
1341 coprocessor. The default is to assume a coprocessor for 68020,
1342 68030, and cpu32. Although the basic 68000 is not compatible with
1343 the 68881, a combination of the two can be specified, since it's
1344 possible to do emulation of the coprocessor instructions with the
1345 main processor.
1346 -m68851 | -mno-68851
1348 The target machine does (or does not) have a memory-management unit
1349 coprocessor. The default is to assume an MMU for 68020 and up.
1350 The following options are available when as is configured for an Altera
1352 Nios II processor.
1353 -relax-section
1355 Replace identified out-of-range branches with PC-relative "jmp"
1356 sequences when possible. The generated code sequences are suitable
1357 for use in position-independent code, but there is a practical
1358 limit on the extended branch range because of the length of the
1359 sequences. This option is the default.
1360 -relax-all
1362 Replace branch instructions not determinable to be in range and all
1363 call instructions with "jmp" and "callr" sequences (respectively).
1364 This option generates absolute relocations against the target
1365 symbols and is not appropriate for position-independent code.
1366 -no-relax
1368 Do not replace any branches or calls.
1369 -EB Generate big-endian output.
1371 -EL Generate little-endian output. This is the default.
1373 -march=architecture
1375 This option specifies the target architecture. The assembler
1376 issues an error message if an attempt is made to assemble an
1377 instruction which will not execute on the target architecture. The
1378 following architecture names are recognized: "r1", "r2". The
1379 default is "r1".
1380 The following options are available when as is configured for a PRU
1382 processor.
1383 -mlink-relax
1385 Assume that LD would optimize LDI32 instructions by checking the
1386 upper 16 bits of the expression. If they are all zeros, then LD
1387 would shorten the LDI32 instruction to a single LDI. In such case
1388 "as" will output DIFF relocations for diff expressions.
1389 -mno-link-relax
1391 Assume that LD would not optimize LDI32 instructions. As a
1392 consequence, DIFF relocations will not be emitted.
1393 -mno-warn-regname-label
1395 Do not warn if a label name matches a register name. Usually
1396 assembler programmers will want this warning to be emitted. C
1397 compilers may want to turn this off.
1398 The following options are available when as is configured for a MIPS
1400 processor.
1401 -G num
1403 This option sets the largest size of an object that can be
1404 referenced implicitly with the "gp" register. It is only accepted
1405 for targets that use ECOFF format, such as a DECstation running
1406 Ultrix. The default value is 8.
1407 -EB Generate "big endian" format output.
1409 -EL Generate "little endian" format output.
1411 -mips1
1413 -mips2
1414 -mips3
1415 -mips4
1416 -mips5
1417 -mips32
1418 -mips32r2
1419 -mips32r3
1420 -mips32r5
1421 -mips32r6
1422 -mips64
1423 -mips64r2
1424 -mips64r3
1425 -mips64r5
1426 -mips64r6
1427 Generate code for a particular MIPS Instruction Set Architecture
1428 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1429 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1430 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1431 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1432 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1433 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1434 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1435 Release 6 ISA processors, respectively.
1436 -march=cpu
1438 Generate code for a particular MIPS CPU.
1439 -mtune=cpu
1441 Schedule and tune for a particular MIPS CPU.
1442 -mfix7000
1444 -mno-fix7000
1445 Cause nops to be inserted if the read of the destination register
1446 of an mfhi or mflo instruction occurs in the following two
1447 instructions.
1448 -mfix-rm7000
1450 -mno-fix-rm7000
1451 Cause nops to be inserted if a dmult or dmultu instruction is
1452 followed by a load instruction.
1453 -mfix-r5900
1455 -mno-fix-r5900
1456 Do not attempt to schedule the preceding instruction into the delay
1457 slot of a branch instruction placed at the end of a short loop of
1458 six instructions or fewer and always schedule a "nop" instruction
1459 there instead. The short loop bug under certain conditions causes
1460 loops to execute only once or twice, due to a hardware bug in the
1461 R5900 chip.
1462 -mdebug
1464 -no-mdebug
1465 Cause stabs-style debugging output to go into an ECOFF-style
1466 .mdebug section instead of the standard ELF .stabs sections.
1467 -mpdr
1469 -mno-pdr
1470 Control generation of ".pdr" sections.
1471 -mgp32
1473 -mfp32
1474 The register sizes are normally inferred from the ISA and ABI, but
1475 these flags force a certain group of registers to be treated as 32
1476 bits wide at all times. -mgp32 controls the size of general-
1477 purpose registers and -mfp32 controls the size of floating-point
1478 registers.
1479 -mgp64
1481 -mfp64
1482 The register sizes are normally inferred from the ISA and ABI, but
1483 these flags force a certain group of registers to be treated as 64
1484 bits wide at all times. -mgp64 controls the size of general-
1485 purpose registers and -mfp64 controls the size of floating-point
1486 registers.
1487 -mfpxx
1489 The register sizes are normally inferred from the ISA and ABI, but
1490 using this flag in combination with -mabi=32 enables an ABI variant
1491 which will operate correctly with floating-point registers which
1492 are 32 or 64 bits wide.
1493 -modd-spreg
1495 -mno-odd-spreg
1496 Enable use of floating-point operations on odd-numbered single-
1497 precision registers when supported by the ISA. -mfpxx implies
1498 -mno-odd-spreg, otherwise the default is -modd-spreg.
1499 -mips16
1501 -no-mips16
1502 Generate code for the MIPS 16 processor. This is equivalent to
1503 putting ".module mips16" at the start of the assembly file.
1504 -no-mips16 turns off this option.
1505 -mmips16e2
1507 -mno-mips16e2
1508 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1509 equivalent to putting ".module mips16e2" at the start of the
1510 assembly file. -mno-mips16e2 turns off this option.
1511 -mmicromips
1513 -mno-micromips
1514 Generate code for the microMIPS processor. This is equivalent to
1515 putting ".module micromips" at the start of the assembly file.
1516 -mno-micromips turns off this option. This is equivalent to
1517 putting ".module nomicromips" at the start of the assembly file.
1518 -msmartmips
1520 -mno-smartmips
1521 Enables the SmartMIPS extension to the MIPS32 instruction set.
1522 This is equivalent to putting ".module smartmips" at the start of
1523 the assembly file. -mno-smartmips turns off this option.
1524 -mips3d
1526 -no-mips3d
1527 Generate code for the MIPS-3D Application Specific Extension. This
1528 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1529 turns off this option.
1530 -mdmx
1532 -no-mdmx
1533 Generate code for the MDMX Application Specific Extension. This
1534 tells the assembler to accept MDMX instructions. -no-mdmx turns
1535 off this option.
1536 -mdsp
1538 -mno-dsp
1539 Generate code for the DSP Release 1 Application Specific Extension.
1540 This tells the assembler to accept DSP Release 1 instructions.
1541 -mno-dsp turns off this option.
1542 -mdspr2
1544 -mno-dspr2
1545 Generate code for the DSP Release 2 Application Specific Extension.
1546 This option implies -mdsp. This tells the assembler to accept DSP
1547 Release 2 instructions. -mno-dspr2 turns off this option.
1548 -mdspr3
1550 -mno-dspr3
1551 Generate code for the DSP Release 3 Application Specific Extension.
1552 This option implies -mdsp and -mdspr2. This tells the assembler to
1553 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1554 option.
1555 -mmsa
1557 -mno-msa
1558 Generate code for the MIPS SIMD Architecture Extension. This tells
1559 the assembler to accept MSA instructions. -mno-msa turns off this
1560 option.
1561 -mxpa
1563 -mno-xpa
1564 Generate code for the MIPS eXtended Physical Address (XPA)
1565 Extension. This tells the assembler to accept XPA instructions.
1566 -mno-xpa turns off this option.
1567 -mmt
1569 -mno-mt
1570 Generate code for the MT Application Specific Extension. This
1571 tells the assembler to accept MT instructions. -mno-mt turns off
1572 this option.
1573 -mmcu
1575 -mno-mcu
1576 Generate code for the MCU Application Specific Extension. This
1577 tells the assembler to accept MCU instructions. -mno-mcu turns off
1578 this option.
1579 -mcrc
1581 -mno-crc
1582 Generate code for the MIPS cyclic redundancy check (CRC)
1583 Application Specific Extension. This tells the assembler to accept
1584 CRC instructions. -mno-crc turns off this option.
1585 -mginv
1587 -mno-ginv
1588 Generate code for the Global INValidate (GINV) Application Specific
1589 Extension. This tells the assembler to accept GINV instructions.
1590 -mno-ginv turns off this option.
1591 -mloongson-mmi
1593 -mno-loongson-mmi
1594 Generate code for the Loongson MultiMedia extensions Instructions
1595 (MMI) Application Specific Extension. This tells the assembler to
1596 accept MMI instructions. -mno-loongson-mmi turns off this option.
1597 -mloongson-cam
1599 -mno-loongson-cam
1600 Generate code for the Loongson Content Address Memory (CAM)
1601 instructions. This tells the assembler to accept Loongson CAM
1602 instructions. -mno-loongson-cam turns off this option.
1603 -mloongson-ext
1605 -mno-loongson-ext
1606 Generate code for the Loongson EXTensions (EXT) instructions. This
1607 tells the assembler to accept Loongson EXT instructions.
1608 -mno-loongson-ext turns off this option.
1609 -mloongson-ext2
1611 -mno-loongson-ext2
1612 Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1613 This option implies -mloongson-ext. This tells the assembler to
1614 accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off
1615 this option.
1616 -minsn32
1618 -mno-insn32
1619 Only use 32-bit instruction encodings when generating code for the
1620 microMIPS processor. This option inhibits the use of any 16-bit
1621 instructions. This is equivalent to putting ".set insn32" at the
1622 start of the assembly file. -mno-insn32 turns off this option.
1623 This is equivalent to putting ".set noinsn32" at the start of the
1624 assembly file. By default -mno-insn32 is selected, allowing all
1625 instructions to be used.
1626 --construct-floats
1628 --no-construct-floats
1629 The --no-construct-floats option disables the construction of
1630 double width floating point constants by loading the two halves of
1631 the value into the two single width floating point registers that
1632 make up the double width register. By default --construct-floats
1633 is selected, allowing construction of these floating point
1634 constants.
1635 --relax-branch
1637 --no-relax-branch
1638 The --relax-branch option enables the relaxation of out-of-range
1639 branches. By default --no-relax-branch is selected, causing any
1640 out-of-range branches to produce an error.
1641 -mignore-branch-isa
1643 -mno-ignore-branch-isa
1644 Ignore branch checks for invalid transitions between ISA modes.
1645 The semantics of branches does not provide for an ISA mode switch,
1646 so in most cases the ISA mode a branch has been encoded for has to
1647 be the same as the ISA mode of the branch's target label.
1648 Therefore GAS has checks implemented that verify in branch assembly
1649 that the two ISA modes match. -mignore-branch-isa disables these
1650 checks. By default -mno-ignore-branch-isa is selected, causing any
1651 invalid branch requiring a transition between ISA modes to produce
1652 an error.
1653 -mnan=encoding
1655 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1656 (-mnan=legacy) NaN encoding format. The latter is the default.
1657 --emulation=name
1659 This option was formerly used to switch between ELF and ECOFF
1660 output on targets like IRIX 5 that supported both. MIPS ECOFF
1661 support was removed in GAS 2.24, so the option now serves little
1662 purpose. It is retained for backwards compatibility.
1663 The available configuration names are: mipself, mipslelf and
1665 mipsbelf. Choosing mipself now has no effect, since the output is
1666 always ELF. mipslelf and mipsbelf select little- and big-endian
1667 output respectively, but -EL and -EB are now the preferred options
1668 instead.
1669 -nocpp
1671 as ignores this option. It is accepted for compatibility with the
1672 native tools.
1673 --trap
1675 --no-trap
1676 --break
1677 --no-break
1678 Control how to deal with multiplication overflow and division by
1679 zero. --trap or --no-break (which are synonyms) take a trap
1680 exception (and only work for Instruction Set Architecture level 2
1681 and higher); --break or --no-trap (also synonyms, and the default)
1682 take a break exception.
1683 -n When this option is used, as will issue a warning every time it
1685 generates a nop instruction from a macro.
1686 The following options are available when as is configured for a Meta
1688 processor.
1689 "-mcpu=metac11"
1691 Generate code for Meta 1.1.
1692 "-mcpu=metac12"
1694 Generate code for Meta 1.2.
1695 "-mcpu=metac21"
1697 Generate code for Meta 2.1.
1698 "-mfpu=metac21"
1700 Allow code to use FPU hardware of Meta 2.1.
1701 See the info pages for documentation of the MMIX-specific options.
1703 The following options are available when as is configured for a NDS32
1705 processor.
1706 "-O1"
1708 Optimize for performance.
1709 "-Os"
1711 Optimize for space.
1712 "-EL"
1714 Produce little endian data output.
1715 "-EB"
1717 Produce little endian data output.
1718 "-mpic"
1720 Generate PIC.
1721 "-mno-fp-as-gp-relax"
1723 Suppress fp-as-gp relaxation for this file.
1724 "-mb2bb-relax"
1726 Back-to-back branch optimization.
1727 "-mno-all-relax"
1729 Suppress all relaxation for this file.
1730 "-march=<arch name>"
1732 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1733 v3f, v3s, v2, v2j, v2f, v2s.
1734 "-mbaseline=<baseline>"
1736 Assemble for baseline <baseline> which could be v2, v3, v3m.
1737 "-mfpu-freg=FREG"
1739 Specify a FPU configuration.
1740 "0 8 SP / 4 DP registers"
1742 "1 16 SP / 8 DP registers"
1743 "2 32 SP / 16 DP registers"
1744 "3 32 SP / 32 DP registers"
1745 "-mabi=abi"
1746 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1747 "-m[no-]mac"
1749 Enable/Disable Multiply instructions support.
1750 "-m[no-]div"
1752 Enable/Disable Divide instructions support.
1753 "-m[no-]16bit-ext"
1755 Enable/Disable 16-bit extension
1756 "-m[no-]dx-regs"
1758 Enable/Disable d0/d1 registers
1759 "-m[no-]perf-ext"
1761 Enable/Disable Performance extension
1762 "-m[no-]perf2-ext"
1764 Enable/Disable Performance extension 2
1765 "-m[no-]string-ext"
1767 Enable/Disable String extension
1768 "-m[no-]reduced-regs"
1770 Enable/Disable Reduced Register configuration (GPR16) option
1771 "-m[no-]audio-isa-ext"
1773 Enable/Disable AUDIO ISA extension
1774 "-m[no-]fpu-sp-ext"
1776 Enable/Disable FPU SP extension
1777 "-m[no-]fpu-dp-ext"
1779 Enable/Disable FPU DP extension
1780 "-m[no-]fpu-fma"
1782 Enable/Disable FPU fused-multiply-add instructions
1783 "-mall-ext"
1785 Turn on all extensions and instructions support
1786 The following options are available when as is configured for a PowerPC
1788 processor.
1789 -a32
1791 Generate ELF32 or XCOFF32.
1792 -a64
1794 Generate ELF64 or XCOFF64.
1795 -K PIC
1797 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1798 -mpwrx | -mpwr2
1800 Generate code for POWER/2 (RIOS2).
1801 -mpwr
1803 Generate code for POWER (RIOS1)
1804 -m601
1806 Generate code for PowerPC 601.
1807 -mppc, -mppc32, -m603, -m604
1809 Generate code for PowerPC 603/604.
1810 -m403, -m405
1812 Generate code for PowerPC 403/405.
1813 -m440
1815 Generate code for PowerPC 440. BookE and some 405 instructions.
1816 -m464
1818 Generate code for PowerPC 464.
1819 -m476
1821 Generate code for PowerPC 476.
1822 -m7400, -m7410, -m7450, -m7455
1824 Generate code for PowerPC 7400/7410/7450/7455.
1825 -m750cl, -mgekko, -mbroadway
1827 Generate code for PowerPC 750CL/Gekko/Broadway.
1828 -m821, -m850, -m860
1830 Generate code for PowerPC 821/850/860.
1831 -mppc64, -m620
1833 Generate code for PowerPC 620/625/630.
1834 -me500, -me500x2
1836 Generate code for Motorola e500 core complex.
1837 -me500mc
1839 Generate code for Freescale e500mc core complex.
1840 -me500mc64
1842 Generate code for Freescale e500mc64 core complex.
1843 -me5500
1845 Generate code for Freescale e5500 core complex.
1846 -me6500
1848 Generate code for Freescale e6500 core complex.
1849 -mspe
1851 Generate code for Motorola SPE instructions.
1852 -mspe2
1854 Generate code for Freescale SPE2 instructions.
1855 -mtitan
1857 Generate code for AppliedMicro Titan core complex.
1858 -mppc64bridge
1860 Generate code for PowerPC 64, including bridge insns.
1861 -mbooke
1863 Generate code for 32-bit BookE.
1864 -ma2
1866 Generate code for A2 architecture.
1867 -me300
1869 Generate code for PowerPC e300 family.
1870 -maltivec
1872 Generate code for processors with AltiVec instructions.
1873 -mvle
1875 Generate code for Freescale PowerPC VLE instructions.
1876 -mvsx
1878 Generate code for processors with Vector-Scalar (VSX) instructions.
1879 -mhtm
1881 Generate code for processors with Hardware Transactional Memory
1882 instructions.
1883 -mpower4, -mpwr4
1885 Generate code for Power4 architecture.
1886 -mpower5, -mpwr5, -mpwr5x
1888 Generate code for Power5 architecture.
1889 -mpower6, -mpwr6
1891 Generate code for Power6 architecture.
1892 -mpower7, -mpwr7
1894 Generate code for Power7 architecture.
1895 -mpower8, -mpwr8
1897 Generate code for Power8 architecture.
1898 -mpower9, -mpwr9
1900 Generate code for Power9 architecture.
1901 -mpower10, -mpwr10
1903 Generate code for Power10 architecture.
1904 -mcell
1906 -mcell
1907 Generate code for Cell Broadband Engine architecture.
1908 -mcom
1910 Generate code Power/PowerPC common instructions.
1911 -many
1913 Generate code for any architecture (PWR/PWRX/PPC).
1914 -mregnames
1916 Allow symbolic names for registers.
1917 -mno-regnames
1919 Do not allow symbolic names for registers.
1920 -mrelocatable
1922 Support for GCC's -mrelocatable option.
1923 -mrelocatable-lib
1925 Support for GCC's -mrelocatable-lib option.
1926 -memb
1928 Set PPC_EMB bit in ELF flags.
1929 -mlittle, -mlittle-endian, -le
1931 Generate code for a little endian machine.
1932 -mbig, -mbig-endian, -be
1934 Generate code for a big endian machine.
1935 -msolaris
1937 Generate code for Solaris.
1938 -mno-solaris
1940 Do not generate code for Solaris.
1941 -nops=count
1943 If an alignment directive inserts more than count nops, put a
1944 branch at the beginning to skip execution of the nops.
1945 The following options are available when as is configured for a RISC-V
1947 processor.
1948 -fpic
1950 -fPIC
1951 Generate position-independent code
1952 -fno-pic
1954 Don't generate position-independent code (default)
1955 -march=ISA
1957 Select the base isa, as specified by ISA. For example
1958 -march=rv32ima. If this option and the architecture attributes
1959 aren't set, then assembler will check the default configure setting
1960 --with-arch=ISA.
1961 -misa-spec=ISAspec
1963 Select the default isa spec version. If the version of ISA isn't
1964 set by -march, then assembler helps to set the version according to
1965 the default chosen spec. If this option isn't set, then assembler
1966 will check the default configure setting --with-isa-spec=ISAspec.
1967 -mpriv-spec=PRIVspec
1969 Select the privileged spec version. We can decide whether the CSR
1970 is valid or not according to the chosen spec. If this option and
1971 the privilege attributes aren't set, then assembler will check the
1972 default configure setting --with-priv-spec=PRIVspec.
1973 -mabi=ABI
1975 Selects the ABI, which is either "ilp32" or "lp64", optionally
1976 followed by "f", "d", or "q" to indicate single-precision, double-
1977 precision, or quad-precision floating-point calling convention, or
1978 none to indicate the soft-float calling convention. Also, "ilp32"
1979 can optionally be followed by "e" to indicate the RVE ABI, which is
1980 always soft-float.
1981 -mrelax
1983 Take advantage of linker relaxations to reduce the number of
1984 instructions required to materialize symbol addresses. (default)
1985 -mno-relax
1987 Don't do linker relaxations.
1988 -march-attr
1990 Generate the default contents for the riscv elf attribute section
1991 if the .attribute directives are not set. This section is used to
1992 record the information that a linker or runtime loader needs to
1993 check compatibility. This information includes ISA string, stack
1994 alignment requirement, unaligned memory accesses, and the major,
1995 minor and revision version of privileged specification.
1996 -mno-arch-attr
1998 Don't generate the default riscv elf attribute section if the
1999 .attribute directives are not set.
2000 -mcsr-check
2002 Enable the CSR checking for the ISA-dependent CRS and the read-only
2003 CSR. The ISA-dependent CSR are only valid when the specific ISA is
2004 set. The read-only CSR can not be written by the CSR instructions.
2005 -mno-csr-check
2007 Don't do CSR checking.
2008 -mlittle-endian
2010 Generate code for a little endian machine.
2011 -mbig-endian
2013 Generate code for a big endian machine.
2014 See the info pages for documentation of the RX-specific options.
2016 The following options are available when as is configured for the s390
2018 processor family.
2019 -m31
2021 -m64
2022 Select the word size, either 31/32 bits or 64 bits.
2023 -mesa
2025 -mzarch
2026 Select the architecture mode, either the Enterprise System
2027 Architecture (esa) or the z/Architecture mode (zarch).
2028 -march=processor
2030 Specify which s390 processor variant is the target, g5 (or arch3),
2031 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2032 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2033 z14 (or arch12), or z15 (or arch13).
2034 -mregnames
2036 -mno-regnames
2037 Allow or disallow symbolic names for registers.
2038 -mwarn-areg-zero
2040 Warn whenever the operand for a base or index register has been
2041 specified but evaluates to zero.
2042 The following options are available when as is configured for a
2044 TMS320C6000 processor.
2045 -march=arch
2047 Enable (only) instructions from architecture arch. By default, all
2048 instructions are permitted.
2049 The following values of arch are accepted: "c62x", "c64x", "c64x+",
2051 "c67x", "c67x+", "c674x".
2052 -mdsbt
2054 -mno-dsbt
2055 The -mdsbt option causes the assembler to generate the
2056 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2057 code is using DSBT addressing. The -mno-dsbt option, the default,
2058 causes the tag to have a value of 0, indicating that the code does
2059 not use DSBT addressing. The linker will emit a warning if objects
2060 of different type (DSBT and non-DSBT) are linked together.
2061 -mpid=no
2063 -mpid=near
2064 -mpid=far
2065 The -mpid= option causes the assembler to generate the
2066 "Tag_ABI_PID" attribute with a value indicating the form of data
2067 addressing used by the code. -mpid=no, the default, indicates
2068 position-dependent data addressing, -mpid=near indicates position-
2069 independent addressing with GOT accesses using near DP addressing,
2070 and -mpid=far indicates position-independent addressing with GOT
2071 accesses using far DP addressing. The linker will emit a warning
2072 if objects built with different settings of this option are linked
2073 together.
2074 -mpic
2076 -mno-pic
2077 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2078 attribute with a value of 1, indicating that the code is using
2079 position-independent code addressing, The "-mno-pic" option, the
2080 default, causes the tag to have a value of 0, indicating position-
2081 dependent code addressing. The linker will emit a warning if
2082 objects of different type (position-dependent and position-
2083 independent) are linked together.
2084 -mbig-endian
2086 -mlittle-endian
2087 Generate code for the specified endianness. The default is little-
2088 endian.
2089 The following options are available when as is configured for a TILE-Gx
2091 processor.
2092 -m32 | -m64
2094 Select the word size, either 32 bits or 64 bits.
2095 -EB | -EL
2097 Select the endianness, either big-endian (-EB) or little-endian
2098 (-EL).
2099 The following option is available when as is configured for a Visium
2101 processor.
2102 -mtune=arch
2104 This option specifies the target architecture. If an attempt is
2105 made to assemble an instruction that will not execute on the target
2106 architecture, the assembler will issue an error message.
2107 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2109 The following options are available when as is configured for an Xtensa
2111 processor.
2112 --text-section-literals | --no-text-section-literals
2114 Control the treatment of literal pools. The default is
2115 --no-text-section-literals, which places literals in separate
2116 sections in the output file. This allows the literal pool to be
2117 placed in a data RAM/ROM. With --text-section-literals, the
2118 literals are interspersed in the text section in order to keep them
2119 as close as possible to their references. This may be necessary
2120 for large assembly files, where the literals would otherwise be out
2121 of range of the "L32R" instructions in the text section. Literals
2122 are grouped into pools following ".literal_position" directives or
2123 preceding "ENTRY" instructions. These options only affect literals
2124 referenced via PC-relative "L32R" instructions; literals for
2125 absolute mode "L32R" instructions are handled separately.
2126 --auto-litpools | --no-auto-litpools
2128 Control the treatment of literal pools. The default is
2129 --no-auto-litpools, which in the absence of --text-section-literals
2130 places literals in separate sections in the output file. This
2131 allows the literal pool to be placed in a data RAM/ROM. With
2132 --auto-litpools, the literals are interspersed in the text section
2133 in order to keep them as close as possible to their references,
2134 explicit ".literal_position" directives are not required. This may
2135 be necessary for very large functions, where single literal pool at
2136 the beginning of the function may not be reachable by "L32R"
2137 instructions at the end. These options only affect literals
2138 referenced via PC-relative "L32R" instructions; literals for
2139 absolute mode "L32R" instructions are handled separately. When
2140 used together with --text-section-literals, --auto-litpools takes
2141 precedence.
2142 --absolute-literals | --no-absolute-literals
2144 Indicate to the assembler whether "L32R" instructions use absolute
2145 or PC-relative addressing. If the processor includes the absolute
2146 addressing option, the default is to use absolute "L32R"
2147 relocations. Otherwise, only the PC-relative "L32R" relocations
2148 can be used.
2149 --target-align | --no-target-align
2151 Enable or disable automatic alignment to reduce branch penalties at
2152 some expense in code size. This optimization is enabled by
2153 default. Note that the assembler will always align instructions
2154 like "LOOP" that have fixed alignment requirements.
2155 --longcalls | --no-longcalls
2157 Enable or disable transformation of call instructions to allow
2158 calls across a greater range of addresses. This option should be
2159 used when call targets can potentially be out of range. It may
2160 degrade both code size and performance, but the linker can
2161 generally optimize away the unnecessary overhead when a call ends
2162 up within range. The default is --no-longcalls.
2163 --transform | --no-transform
2165 Enable or disable all assembler transformations of Xtensa
2166 instructions, including both relaxation and optimization. The
2167 default is --transform; --no-transform should only be used in the
2168 rare cases when the instructions must be exactly as specified in
2169 the assembly source. Using --no-transform causes out of range
2170 instruction operands to be errors.
2171 --rename-section oldname=newname
2173 Rename the oldname section to newname. This option can be used
2174 multiple times to rename multiple sections.
2175 --trampolines | --no-trampolines
2177 Enable or disable transformation of jump instructions to allow
2178 jumps across a greater range of addresses. This option should be
2179 used when jump targets can potentially be out of range. In the
2180 absence of such jumps this option does not affect code size or
2181 performance. The default is --trampolines.
2182 --abi-windowed | --abi-call0
2184 Choose ABI tag written to the ".xtensa.info" section. ABI tag
2185 indicates ABI of the assembly code. A warning is issued by the
2186 linker on an attempt to link object files with inconsistent ABI
2187 tags. Default ABI is chosen by the Xtensa core configuration.
2188 The following options are available when as is configured for an Z80
2190 processor.
2191 @chapter Z80 Dependent Features
2193 Command-line Options
2195 -march=CPU[-EXT...][+EXT...]
2196 This option specifies the target processor. The assembler will
2197 issue an error message if an attempt is made to assemble an
2198 instruction which will not execute on the target processor. The
2199 following processor names are recognized: "z80", "z180", "ez80",
2200 "gbz80", "z80n", "r800". In addition to the basic instruction set,
2201 the assembler can be told to accept some extention mnemonics. For
2202 example, "-march=z180+sli+infc" extends z180 with SLI instructions
2203 and IN F,(C). The following extentions are currently supported:
2204 "full" (all known instructions), "adl" (ADL CPU mode by default,
2205 eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2206 (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2207 "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2208 "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2209 (C),0). Note that rather than extending a basic instruction set,
2210 the extention mnemonics starting with "-" revoke the respective
2211 functionality: "-march=z80-full+xyhl" first removes all default
2212 extentions and adds support for index registers halves only.
2213 If this option is not specified then "-march=z80+xyhl+infc" is
2215 assumed.
2216 -local-prefix=prefix
2218 Mark all labels with specified prefix as local. But such label can
2219 be marked global explicitly in the code. This option do not change
2220 default local label prefix ".L", it is just adds new one.
2221 -colonless
2223 Accept colonless labels. All symbols at line begin are treated as
2224 labels.
2225 -sdcc
2227 Accept assembler code produced by SDCC.
2228 -fp-s=FORMAT
2230 Single precision floating point numbers format. Default: ieee754
2231 (32 bit).
2232 -fp-d=FORMAT
2234 Double precision floating point numbers format. Default: ieee754
2235 (64 bit).
2236
2238 gcc(1), ld(1), and the Info entries for binutils and ld.
2239
2241 Copyright (c) 1991-2021 Free Software Foundation, Inc.
2242 Permission is granted to copy, distribute and/or modify this document
2244 under the terms of the GNU Free Documentation License, Version 1.3 or
2245 any later version published by the Free Software Foundation; with no
2246 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2247 Texts. A copy of the license is included in the section entitled "GNU
2248 Free Documentation License".
2249binutils-2.37 2022-03-10 AS(1)