1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-<N>] [--gdwarf-sections]
14 [--gdwarf-cie-version=VERSION]
15 [--help] [-I dir] [-J]
16 [-K] [-L] [--listing-lhs-width=NUM]
17 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18 [--listing-cont-lines=NUM] [--keep-locals]
19 [--no-pad-sections]
20 [-o objfile] [-R]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--generate-missing-build-notes=[no|yes]]
28 [--multibyte-handling=[allow|warn|warn-sym-only]]
29 [--target-help] [target-options]
30 [--|files ...]
31
33 Target AArch64 options:
34 [-EB|-EL]
35 [-mabi=ABI]
36 Target Alpha options:
38 [-mcpu]
39 [-mdebug | -no-mdebug]
40 [-replace | -noreplace]
41 [-relax] [-g] [-Gsize]
42 [-F] [-32addr]
43 Target ARC options:
45 [-mcpu=cpu]
46 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
47 [-mcode-density]
48 [-mrelax]
49 [-EB|-EL]
50 Target ARM options:
52 [-mcpu=processor[+extension...]]
53 [-march=architecture[+extension...]]
54 [-mfpu=floating-point-format]
55 [-mfloat-abi=abi]
56 [-meabi=ver]
57 [-mthumb]
58 [-EB|-EL]
59 [-mapcs-32|-mapcs-26|-mapcs-float|
60 -mapcs-reentrant]
61 [-mthumb-interwork] [-k]
62 Target Blackfin options:
64 [-mcpu=processor[-sirevision]]
65 [-mfdpic]
66 [-mno-fdpic]
67 [-mnopic]
68 Target BPF options:
70 [-EL] [-EB]
71 Target CRIS options:
73 [--underscore | --no-underscore]
74 [--pic] [-N]
75 [--emulation=criself | --emulation=crisaout]
76 [--march=v0_v10 | --march=v10 | --march=v32 |
77 --march=common_v10_v32]
78 Target C-SKY options:
80 [-march=arch] [-mcpu=cpu]
81 [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
82 [-fpic] [-pic]
83 [-mljump] [-mno-ljump]
84 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
85 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
86 [-mnolrw ] [-mno-lrw]
87 [-melrw] [-mno-elrw]
88 [-mlaf ] [-mliterals-after-func]
89 [-mno-laf] [-mno-literals-after-func]
90 [-mlabr] [-mliterals-after-br]
91 [-mno-labr] [-mnoliterals-after-br]
92 [-mistack] [-mno-istack]
93 [-mhard-float] [-mmp] [-mcp] [-mcache]
94 [-msecurity] [-mtrust]
95 [-mdsp] [-medsp] [-mvdsp]
96 Target D10V options:
98 [-O]
99 Target D30V options:
101 [-O|-n|-N]
102 Target EPIPHANY options:
104 [-mepiphany|-mepiphany16]
105 Target H8/300 options:
107 [-h-tick-hex]
108 Target i386 options:
110 [--32|--x32|--64] [-n]
111 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
112 Target IA-64 options:
114 [-mconstant-gp|-mauto-pic]
115 [-milp32|-milp64|-mlp64|-mp64]
116 [-mle|mbe]
117 [-mtune=itanium1|-mtune=itanium2]
118 [-munwind-check=warning|-munwind-check=error]
119 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
120 [-x|-xexplicit] [-xauto] [-xdebug]
121 Target IP2K options:
123 [-mip2022|-mip2022ext]
124 Target M32C options:
126 [-m32c|-m16c] [-relax] [-h-tick-hex]
127 Target M32R options:
129 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
130 --W[n]p]
131 Target M680X0 options:
133 [-l] [-m68000|-m68010|-m68020|...]
134 Target M68HC11 options:
136 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
137 [-mshort|-mlong]
138 [-mshort-double|-mlong-double]
139 [--force-long-branches] [--short-branches]
140 [--strict-direct-mode] [--print-insn-syntax]
141 [--print-opcodes] [--generate-example]
142 Target MCORE options:
144 [-jsri2bsr] [-sifilter] [-relax]
145 [-mcpu=[210|340]]
146 Target Meta options:
148 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
149 Target MIPS options:
151 [-nocpp] [-EL] [-EB] [-O[optimization level]]
152 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
153 [-non_shared] [-xgot [-mvxworks-pic]
154 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
155 [-mfp64] [-mgp64] [-mfpxx]
156 [-modd-spreg] [-mno-odd-spreg]
157 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
158 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
159 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
160 [-mips64r3] [-mips64r5] [-mips64r6]
161 [-construct-floats] [-no-construct-floats]
162 [-mignore-branch-isa] [-mno-ignore-branch-isa]
163 [-mnan=encoding]
164 [-trap] [-no-break] [-break] [-no-trap]
165 [-mips16] [-no-mips16]
166 [-mmips16e2] [-mno-mips16e2]
167 [-mmicromips] [-mno-micromips]
168 [-msmartmips] [-mno-smartmips]
169 [-mips3d] [-no-mips3d]
170 [-mdmx] [-no-mdmx]
171 [-mdsp] [-mno-dsp]
172 [-mdspr2] [-mno-dspr2]
173 [-mdspr3] [-mno-dspr3]
174 [-mmsa] [-mno-msa]
175 [-mxpa] [-mno-xpa]
176 [-mmt] [-mno-mt]
177 [-mmcu] [-mno-mcu]
178 [-mcrc] [-mno-crc]
179 [-mginv] [-mno-ginv]
180 [-mloongson-mmi] [-mno-loongson-mmi]
181 [-mloongson-cam] [-mno-loongson-cam]
182 [-mloongson-ext] [-mno-loongson-ext]
183 [-mloongson-ext2] [-mno-loongson-ext2]
184 [-minsn32] [-mno-insn32]
185 [-mfix7000] [-mno-fix7000]
186 [-mfix-rm7000] [-mno-fix-rm7000]
187 [-mfix-vr4120] [-mno-fix-vr4120]
188 [-mfix-vr4130] [-mno-fix-vr4130]
189 [-mfix-r5900] [-mno-fix-r5900]
190 [-mdebug] [-no-mdebug]
191 [-mpdr] [-mno-pdr]
192 Target MMIX options:
194 [--fixed-special-register-names] [--globalize-symbols]
195 [--gnu-syntax] [--relax] [--no-predefined-symbols]
196 [--no-expand] [--no-merge-gregs] [-x]
197 [--linker-allocated-gregs]
198 Target Nios II options:
200 [-relax-all] [-relax-section] [-no-relax]
201 [-EB] [-EL]
202 Target NDS32 options:
204 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
205 [-misa=isa] [-mabi=abi] [-mall-ext]
206 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
207 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
208 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
209 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
210 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
211 [-mb2bb]
212 Target PDP11 options:
214 [-mpic|-mno-pic] [-mall] [-mno-extensions]
215 [-mextension|-mno-extension]
216 [-mcpu] [-mmachine]
217 Target picoJava options:
219 [-mb|-me]
220 Target PowerPC options:
222 [-a32|-a64]
223 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
224 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
225 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
226 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
227 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
228 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
229 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
230 [-mregnames|-mno-regnames]
231 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
232 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
233 [-msolaris|-mno-solaris]
234 [-nops=count]
235 Target PRU options:
237 [-link-relax]
238 [-mnolink-relax]
239 [-mno-warn-regname-label]
240 Target RISC-V options:
242 [-fpic|-fPIC|-fno-pic]
243 [-march=ISA]
244 [-mabi=ABI]
245 [-mlittle-endian|-mbig-endian]
246 Target RL78 options:
248 [-mg10]
249 [-m32bit-doubles|-m64bit-doubles]
250 Target RX options:
252 [-mlittle-endian|-mbig-endian]
253 [-m32bit-doubles|-m64bit-doubles]
254 [-muse-conventional-section-names]
255 [-msmall-data-limit]
256 [-mpid]
257 [-mrelax]
258 [-mint-register=number]
259 [-mgcc-abi|-mrx-abi]
260 Target s390 options:
262 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
263 [-mregnames|-mno-regnames]
264 [-mwarn-areg-zero]
265 Target SCORE options:
267 [-EB][-EL][-FIXDD][-NWARN]
268 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
269 [-march=score7][-march=score3]
270 [-USE_R1][-KPIC][-O0][-G num][-V]
271 Target SPARC options:
273 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
274 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
275 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
276 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
277 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
278 -Asparcvisr|-Asparc5]
279 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
280 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
281 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
282 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
283 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
284 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
285 -bump]
286 [-32|-64]
287 [--enforce-aligned-data][--dcti-couples-detect]
288 Target TIC54X options:
290 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
291 [-merrors-to-file <filename>|-me <filename>]
292 Target TIC6X options:
294 [-march=arch] [-mbig-endian|-mlittle-endian]
295 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
296 [-mpic|-mno-pic]
297 Target TILE-Gx options:
299 [-m32|-m64][-EB][-EL]
300 Target Visium options:
302 [-mtune=arch]
303 Target Xtensa options:
305 [--[no-]text-section-literals] [--[no-]auto-litpools]
306 [--[no-]absolute-literals]
307 [--[no-]target-align] [--[no-]longcalls]
308 [--[no-]transform]
309 [--rename-section oldname=newname]
310 [--[no-]trampolines]
311 [--abi-windowed|--abi-call0]
312 Target Z80 options:
314 [-march=CPU[-EXT][+EXT]]
315 [-local-prefix=PREFIX]
316 [-colonless]
317 [-sdcc]
318 [-fp-s=FORMAT]
319 [-fp-d=FORMAT]
320
322 GNU as is really a family of assemblers. If you use (or have used) the
323 GNU assembler on one architecture, you should find a fairly similar
324 environment when you use it on another architecture. Each version has
325 much in common with the others, including object file formats, most
326 assembler directives (often called pseudo-ops) and assembler syntax.
327 as is primarily intended to assemble the output of the GNU C compiler
329 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
330 assemble correctly everything that other assemblers for the same
331 machine would assemble. Any exceptions are documented explicitly.
332 This doesn't mean as always uses the same syntax as another assembler
333 for the same architecture; for example, we know of several incompatible
334 versions of 680x0 assembly language syntax.
335 Each time you run as it assembles exactly one source program. The
337 source program is made up of one or more files. (The standard input is
338 also a file.)
339 You give as a command line that has zero or more input file names. The
341 input files are read (from left file name to right). A command-line
342 argument (in any position) that has no special meaning is taken to be
343 an input file name.
344 If you give as no file names it attempts to read one input file from
346 the as standard input, which is normally your terminal. You may have
347 to type ctl-D to tell as there is no more program to assemble.
348 Use -- if you need to explicitly name the standard input file in your
350 command line.
351 If the source is empty, as produces a small, empty object file.
353 as may write warnings and error messages to the standard error file
355 (usually your terminal). This should not happen when a compiler runs
356 as automatically. Warnings report an assumption made so that as could
357 keep assembling a flawed program; errors report a grave problem that
358 stops the assembly.
359 If you are invoking as via the GNU C compiler, you can use the -Wa
361 option to pass arguments through to the assembler. The assembler
362 arguments must be separated from each other (and the -Wa) by commas.
363 For example:
364 gcc -c -g -O -Wa,-alh,-L file.c
366 This passes two options to the assembler: -alh (emit a listing to
368 standard output with high-level and assembly source) and -L (retain
369 local symbols in the symbol table).
370 Usually you do not need to use this -Wa mechanism, since many compiler
372 command-line options are automatically passed to the assembler by the
373 compiler. (You can call the GNU compiler driver with the -v option to
374 see precisely what options it passes to each compilation pass,
375 including the assembler.)
376
378 @file
379 Read command-line options from file. The options read are inserted
380 in place of the original @file option. If file does not exist, or
381 cannot be read, then the option will be treated literally, and not
382 removed.
383 Options in file are separated by whitespace. A whitespace
385 character may be included in an option by surrounding the entire
386 option in either single or double quotes. Any character (including
387 a backslash) may be included by prefixing the character to be
388 included with a backslash. The file may itself contain additional
389 @file options; any such options will be processed recursively.
390 -a[cdghlmns]
392 Turn on listings, in any of a variety of ways:
393 -ac omit false conditionals
395 -ad omit debugging directives
397 -ag include general information, like as version and options passed
399 -ah include high-level source
401 -al include assembly
403 -am include macro expansions
405 -an omit forms processing
407 -as include symbols
409 =file
411 set the name of the listing file
412 You may combine these options; for example, use -aln for assembly
414 listing without forms processing. The =file option, if used, must
415 be the last one. By itself, -a defaults to -ahls.
416 --alternate
418 Begin in alternate macro mode.
419 --compress-debug-sections
421 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
422 the ELF ABI. The resulting object file may not be compatible with
423 older linkers and object file utilities. Note if compression would
424 make a given section larger then it is not compressed.
425 --compress-debug-sections=none
427 --compress-debug-sections=zlib
428 --compress-debug-sections=zlib-gnu
429 --compress-debug-sections=zlib-gabi
430 These options control how DWARF debug sections are compressed.
431 --compress-debug-sections=none is equivalent to
432 --nocompress-debug-sections. --compress-debug-sections=zlib and
433 --compress-debug-sections=zlib-gabi are equivalent to
434 --compress-debug-sections. --compress-debug-sections=zlib-gnu
435 compresses DWARF debug sections using zlib. The debug sections are
436 renamed to begin with .zdebug. Note if compression would make a
437 given section larger then it is not compressed nor renamed.
438 --nocompress-debug-sections
440 Do not compress DWARF debug sections. This is usually the default
441 for all targets except the x86/x86_64, but a configure time option
442 can be used to override this.
443 -D Ignored. This option is accepted for script compatibility with
445 calls to other assemblers.
446 --debug-prefix-map old=new
448 When assembling files in directory old, record debugging
449 information describing them as in new instead.
450 --defsym sym=value
452 Define the symbol sym to be value before assembling the input file.
453 value must be an integer constant. As in C, a leading 0x indicates
454 a hexadecimal value, and a leading 0 indicates an octal value. The
455 value of the symbol can be overridden inside a source file via the
456 use of a ".set" pseudo-op.
457 -f "fast"---skip whitespace and comment preprocessing (assume source
459 is compiler output).
460 -g
462 --gen-debug
463 Generate debugging information for each assembler source line using
464 whichever debug format is preferred by the target. This currently
465 means either STABS, ECOFF or DWARF2. When the debug format is
466 DWARF then a ".debug_info" and ".debug_line" section is only
467 emitted when the assembly file doesn't generate one itself.
468 --gstabs
470 Generate stabs debugging information for each assembler line. This
471 may help debugging assembler code, if the debugger can handle it.
472 --gstabs+
474 Generate stabs debugging information for each assembler line, with
475 GNU extensions that probably only gdb can handle, and that could
476 make other debuggers crash or refuse to read your program. This
477 may help debugging assembler code. Currently the only GNU
478 extension is the location of the current working directory at
479 assembling time.
480 --gdwarf-2
482 Generate DWARF2 debugging information for each assembler line.
483 This may help debugging assembler code, if the debugger can handle
484 it. Note---this option is only supported by some targets, not all
485 of them.
486 --gdwarf-3
488 This option is the same as the --gdwarf-2 option, except that it
489 allows for the possibility of the generation of extra debug
490 information as per version 3 of the DWARF specification. Note -
491 enabling this option does not guarantee the generation of any extra
492 information, the choice to do so is on a per target basis.
493 --gdwarf-4
495 This option is the same as the --gdwarf-2 option, except that it
496 allows for the possibility of the generation of extra debug
497 information as per version 4 of the DWARF specification. Note -
498 enabling this option does not guarantee the generation of any extra
499 information, the choice to do so is on a per target basis.
500 --gdwarf-5
502 This option is the same as the --gdwarf-2 option, except that it
503 allows for the possibility of the generation of extra debug
504 information as per version 5 of the DWARF specification. Note -
505 enabling this option does not guarantee the generation of any extra
506 information, the choice to do so is on a per target basis.
507 --gdwarf-sections
509 Instead of creating a .debug_line section, create a series of
510 .debug_line.foo sections where foo is the name of the corresponding
511 code section. For example a code section called .text.func will
512 have its dwarf line number information placed into a section called
513 .debug_line.text.func. If the code section is just called .text
514 then debug line section will still be called just .debug_line
515 without any suffix.
516 --gdwarf-cie-version=version
518 Control which version of DWARF Common Information Entries (CIEs)
519 are produced. When this flag is not specificed the default is
520 version 1, though some targets can modify this default. Other
521 possible values for version are 3 or 4.
522 --size-check=error
524 --size-check=warning
525 Issue an error or warning for invalid ELF .size directive.
526 --elf-stt-common=no
528 --elf-stt-common=yes
529 These options control whether the ELF assembler should generate
530 common symbols with the "STT_COMMON" type. The default can be
531 controlled by a configure option --enable-elf-stt-common.
532 --generate-missing-build-notes=yes
534 --generate-missing-build-notes=no
535 These options control whether the ELF assembler should generate GNU
536 Build attribute notes if none are present in the input sources.
537 The default can be controlled by the --enable-generate-build-notes
538 configure option.
539 --help
541 Print a summary of the command-line options and exit.
542 --target-help
544 Print a summary of all target specific options and exit.
545 -I dir
547 Add directory dir to the search list for ".include" directives.
548 -J Don't warn about signed overflow.
550 -K Issue warnings when difference tables altered for long
552 displacements.
553 -L
555 --keep-locals
556 Keep (in the symbol table) local symbols. These symbols start with
557 system-specific local label prefixes, typically .L for ELF systems
558 or L for traditional a.out systems.
559 --listing-lhs-width=number
561 Set the maximum width, in words, of the output data column for an
562 assembler listing to number.
563 --listing-lhs-width2=number
565 Set the maximum width, in words, of the output data column for
566 continuation lines in an assembler listing to number.
567 --listing-rhs-width=number
569 Set the maximum width of an input source line, as displayed in a
570 listing, to number bytes.
571 --listing-cont-lines=number
573 Set the maximum number of lines printed in a listing for a single
574 line of input to number + 1.
575 --multibyte-handling=allow
577 --multibyte-handling=warn
578 --multibyte-handling=warn-sym-only
579 Controls how the assembler handles multibyte characters in the
580 input. The default (which can be restored by using the allow
581 argument) is to allow such characters without complaint. Using the
582 warn argument will make the assembler generate a warning message
583 whenever any multibyte character is encountered. Using the warn-
584 sym-only argument will only cause a warning to be generated when a
585 symbol is defined with a name that contains multibyte characters.
586 (References to undefined symbols will not generate a warning).
587 --no-pad-sections
589 Stop the assembler for padding the ends of output sections to the
590 alignment of that section. The default is to pad the sections, but
591 this can waste space which might be needed on targets which have
592 tight memory constraints.
593 -o objfile
595 Name the object-file output from as objfile.
596 -R Fold the data section into the text section.
598 --sectname-subst
600 Honor substitution sequences in section names.
601 --statistics
603 Print the maximum space (in bytes) and total time (in seconds) used
604 by assembly.
605 --strip-local-absolute
607 Remove local absolute symbols from the outgoing symbol table.
608 -v
610 -version
611 Print the as version.
612 --version
614 Print the as version and exit.
615 -W
617 --no-warn
618 Suppress warning messages.
619 --fatal-warnings
621 Treat warnings as errors.
622 --warn
624 Don't suppress warning messages or treat them as errors.
625 -w Ignored.
627 -x Ignored.
629 -Z Generate an object file even after errors.
631 -- | files ...
633 Standard input, or source files to assemble.
634 The following options are available when as is configured for the
636 64-bit mode of the ARM Architecture (AArch64).
637 -EB This option specifies that the output generated by the assembler
639 should be marked as being encoded for a big-endian processor.
640 -EL This option specifies that the output generated by the assembler
642 should be marked as being encoded for a little-endian processor.
643 -mabi=abi
645 Specify which ABI the source code uses. The recognized arguments
646 are: "ilp32" and "lp64", which decides the generated object file in
647 ELF32 and ELF64 format respectively. The default is "lp64".
648 -mcpu=processor[+extension...]
650 This option specifies the target processor. The assembler will
651 issue an error message if an attempt is made to assemble an
652 instruction which will not execute on the target processor. The
653 following processor names are recognized: "cortex-a34",
654 "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
655 "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
656 "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77",
657 "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510",
658 "cortex-a710", "ares", "exynos-m1", "falkor", "neoverse-n1",
659 "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira",
660 "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1",
661 and "cortex-x2". The special name "all" may be used to allow the
662 assembler to accept instructions valid for any supported processor,
663 including all optional extensions.
664 In addition to the basic instruction set, the assembler can be told
666 to accept, or restrict, various extension mnemonics that extend the
667 processor.
668 If some implementations of a particular processor can have an
670 extension, then then those extensions are automatically enabled.
671 Consequently, you will not normally have to specify any additional
672 extensions.
673 -march=architecture[+extension...]
675 This option specifies the target architecture. The assembler will
676 issue an error message if an attempt is made to assemble an
677 instruction which will not execute on the target architecture. The
678 following architecture names are recognized: "armv8-a",
679 "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a",
680 "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8-r", "armv9-a",
681 "armv9.1-a", "armv9.2-a", and "armv9.3-a".
682 If both -mcpu and -march are specified, the assembler will use the
684 setting for -mcpu. If neither are specified, the assembler will
685 default to -mcpu=all.
686 The architecture option can be extended with the same instruction
688 set extension options as the -mcpu option. Unlike -mcpu,
689 extensions are not always enabled by default,
690 -mverbose-error
692 This option enables verbose error messages for AArch64 gas. This
693 option is enabled by default.
694 -mno-verbose-error
696 This option disables verbose error messages in AArch64 gas.
697 The following options are available when as is configured for an Alpha
699 processor.
700 -mcpu
702 This option specifies the target processor. If an attempt is made
703 to assemble an instruction which will not execute on the target
704 processor, the assembler may either expand the instruction as a
705 macro or issue an error message. This option is equivalent to the
706 ".arch" directive.
707 The following processor names are recognized: 21064, "21064a",
709 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
710 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
711 "ev67", "ev68". The special name "all" may be used to allow the
712 assembler to accept instructions valid for any Alpha processor.
713 In order to support existing practice in OSF/1 with respect to
715 ".arch", and existing practice within MILO (the Linux ARC
716 bootloader), the numbered processor names (e.g. 21064) enable the
717 processor-specific PALcode instructions, while the "electro-vlasic"
718 names (e.g. "ev4") do not.
719 -mdebug
721 -no-mdebug
722 Enables or disables the generation of ".mdebug" encapsulation for
723 stabs directives and procedure descriptors. The default is to
724 automatically enable ".mdebug" when the first stabs directive is
725 seen.
726 -relax
728 This option forces all relocations to be put into the object file,
729 instead of saving space and resolving some relocations at assembly
730 time. Note that this option does not propagate all symbol
731 arithmetic into the object file, because not all symbol arithmetic
732 can be represented. However, the option can still be useful in
733 specific applications.
734 -replace
736 -noreplace
737 Enables or disables the optimization of procedure calls, both at
738 assemblage and at link time. These options are only available for
739 VMS targets and "-replace" is the default. See section 1.4.1 of
740 the OpenVMS Linker Utility Manual.
741 -g This option is used when the compiler generates debug information.
743 When gcc is using mips-tfile to generate debug information for
744 ECOFF, local labels must be passed through to the object file.
745 Otherwise this option has no effect.
746 -Gsize
748 A local common symbol larger than size is placed in ".bss", while
749 smaller symbols are placed in ".sbss".
750 -F
752 -32addr
753 These options are ignored for backward compatibility.
754 The following options are available when as is configured for an ARC
756 processor.
757 -mcpu=cpu
759 This option selects the core processor variant.
760 -EB | -EL
762 Select either big-endian (-EB) or little-endian (-EL) output.
763 -mcode-density
765 Enable Code Density extension instructions.
766 The following options are available when as is configured for the ARM
768 processor family.
769 -mcpu=processor[+extension...]
771 Specify which ARM processor variant is the target.
772 -march=architecture[+extension...]
774 Specify which ARM architecture variant is used by the target.
775 -mfpu=floating-point-format
777 Select which Floating Point architecture is the target.
778 -mfloat-abi=abi
780 Select which floating point ABI is in use.
781 -mthumb
783 Enable Thumb only instruction decoding.
784 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
786 Select which procedure calling convention is in use.
787 -EB | -EL
789 Select either big-endian (-EB) or little-endian (-EL) output.
790 -mthumb-interwork
792 Specify that the code has been generated with interworking between
793 Thumb and ARM code in mind.
794 -mccs
796 Turns on CodeComposer Studio assembly syntax compatibility mode.
797 -k Specify that PIC code has been generated.
799 The following options are available when as is configured for the
801 Blackfin processor family.
802 -mcpu=processor[-sirevision]
804 This option specifies the target processor. The optional
805 sirevision is not used in assembler. It's here such that GCC can
806 easily pass down its "-mcpu=" option. The assembler will issue an
807 error message if an attempt is made to assemble an instruction
808 which will not execute on the target processor. The following
809 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
810 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
811 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
812 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
813 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
814 "bf549", "bf549m", "bf561", and "bf592".
815 -mfdpic
817 Assemble for the FDPIC ABI.
818 -mno-fdpic
820 -mnopic
821 Disable -mfdpic.
822 The following options are available when as is configured for the Linux
824 kernel BPF processor family.
825 @chapter BPF Dependent Features
827 Options
829 -EB This option specifies that the assembler should emit big-endian
830 eBPF.
831 -EL This option specifies that the assembler should emit little-endian
833 eBPF.
834 Note that if no endianness option is specified in the command line, the
836 host endianness is used. See the info pages for documentation of the
837 CRIS-specific options.
838 The following options are available when as is configured for the C-SKY
840 processor family.
841 -march=archname
843 Assemble for architecture archname. The --help option lists valid
844 values for archname.
845 -mcpu=cpuname
847 Assemble for architecture cpuname. The --help option lists valid
848 values for cpuname.
849 -EL
851 -mlittle-endian
852 Generate little-endian output.
853 -EB
855 -mbig-endian
856 Generate big-endian output.
857 -fpic
859 -pic
860 Generate position-independent code.
861 -mljump
863 -mno-ljump
864 Enable/disable transformation of the short branch instructions
865 "jbf", "jbt", and "jbr" to "jmpi". This option is for V2
866 processors only. It is ignored on CK801 and CK802 targets, which
867 do not support the "jmpi" instruction, and is enabled by default
868 for other processors.
869 -mbranch-stub
871 -mno-branch-stub
872 Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
873 instructions to the linker.
874 This option is only available for bare-metal C-SKY V2 ELF targets,
876 where it is enabled by default. It cannot be used in code that
877 will be dynamically linked against shared libraries.
878 -force2bsr
880 -mforce2bsr
881 -no-force2bsr
882 -mno-force2bsr
883 Enable/disable transformation of "jbsr" instructions to "bsr".
884 This option is always enabled (and -mno-force2bsr is ignored) for
885 CK801/CK802 targets. It is also always enabled when -mbranch-stub
886 is in effect.
887 -jsri2bsr
889 -mjsri2bsr
890 -no-jsri2bsr
891 -mno-jsri2bsr
892 Enable/disable transformation of "jsri" instructions to "bsr".
893 This option is enabled by default.
894 -mnolrw
896 -mno-lrw
897 Enable/disable transformation of "lrw" instructions into a
898 "movih"/"ori" pair.
899 -melrw
901 -mno-elrw
902 Enable/disable extended "lrw" instructions. This option is enabled
903 by default for CK800-series processors.
904 -mlaf
906 -mliterals-after-func
907 -mno-laf
908 -mno-literals-after-func
909 Enable/disable placement of literal pools after each function.
910 -mlabr
912 -mliterals-after-br
913 -mno-labr
914 -mnoliterals-after-br
915 Enable/disable placement of literal pools after unconditional
916 branches. This option is enabled by default.
917 -mistack
919 -mno-istack
920 Enable/disable interrupt stack instructions. This option is
921 enabled by default on CK801, CK802, and CK802 processors.
922 The following options explicitly enable certain optional instructions.
924 These features are also enabled implicitly by using "-mcpu=" to specify
925 a processor that supports it.
926 -mhard-float
928 Enable hard float instructions.
929 -mmp
931 Enable multiprocessor instructions.
932 -mcp
934 Enable coprocessor instructions.
935 -mcache
937 Enable cache prefetch instruction.
938 -msecurity
940 Enable C-SKY security instructions.
941 -mtrust
943 Enable C-SKY trust instructions.
944 -mdsp
946 Enable DSP instructions.
947 -medsp
949 Enable enhanced DSP instructions.
950 -mvdsp
952 Enable vector DSP instructions.
953 The following options are available when as is configured for an
955 Epiphany processor.
956 -mepiphany
958 Specifies that the both 32 and 16 bit instructions are allowed.
959 This is the default behavior.
960 -mepiphany16
962 Restricts the permitted instructions to just the 16 bit set.
963 The following options are available when as is configured for an H8/300
965 processor. @chapter H8/300 Dependent Features
966 Options
968 The Renesas H8/300 version of "as" has one machine-dependent option:
969 -h-tick-hex
971 Support H'00 style hex constants in addition to 0x00 style.
972 -mach=name
974 Sets the H8300 machine variant. The following machine names are
975 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
976 "h8300sxn".
977 The following options are available when as is configured for an i386
979 processor.
980 --32 | --x32 | --64
982 Select the word size, either 32 bits or 64 bits. --32 implies
983 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
984 architecture with 32-bit or 64-bit word-size respectively.
985 These options are only available with the ELF object file format,
987 and require that the necessary BFD support has been included (on a
988 32-bit platform you have to add --enable-64-bit-bfd to configure
989 enable 64-bit usage and use x86-64 as target platform).
990 -n By default, x86 GAS replaces multiple nop instructions used for
992 alignment within code sections with multi-byte nop instructions
993 such as leal 0(%esi,1),%esi. This switch disables the optimization
994 if a single byte nop (0x90) is explicitly specified as the fill
995 byte for alignment.
996 --divide
998 On SVR4-derived platforms, the character / is treated as a comment
999 character, which means that it cannot be used in expressions. The
1000 --divide option turns / into a normal character. This does not
1001 disable / at the beginning of a line starting a comment, or affect
1002 using # for starting a comment.
1003 -march=CPU[+EXTENSION...]
1005 This option specifies the target processor. The assembler will
1006 issue an error message if an attempt is made to assemble an
1007 instruction which will not execute on the target processor. The
1008 following processor names are recognized: "i8086", "i186", "i286",
1009 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
1010 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
1011 "core", "core2", "corei7", "iamcu", "k6", "k6_2", "athlon",
1012 "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3",
1013 "bdver4", "znver1", "znver2", "znver3", "btver1", "btver2",
1014 "generic32" and "generic64".
1015 In addition to the basic instruction set, the assembler can be told
1017 to accept various extension mnemonics. For example,
1018 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
1019 following extensions are currently supported: 8087, 287, 387, 687,
1020 "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1021 "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1022 "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nosse4a",
1023 "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2",
1024 "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
1025 "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq",
1026 "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b",
1027 "enqcmd", "serialize", "tsxldtrk", "kl", "nokl", "widekl",
1028 "nowidekl", "hreset", "avx512f", "avx512cd", "avx512er",
1029 "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma",
1030 "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
1031 "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1032 "avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni",
1033 "avx512_fp16", "noavx512f", "noavx512cd", "noavx512er",
1034 "noavx512pf", "noavx512vl", "noavx512bw", "noavx512dq",
1035 "noavx512ifma", "noavx512vbmi", "noavx512_4fmaps",
1036 "noavx512_4vnniw", "noavx512_vpopcntdq", "noavx512_vbmi2",
1037 "noavx512_vnni", "noavx512_bitalg", "noavx512_vp2intersect",
1038 "notdx", "noavx512_bf16", "noavx_vnni", "noavx512_fp16",
1039 "noenqcmd", "noserialize", "notsxldtrk", "amx_int8", "noamx_int8",
1040 "amx_bf16", "noamx_bf16", "amx_tile", "noamx_tile", "nouintr",
1041 "nohreset", "vmx", "vmfunc", "smx", "xsave", "xsaveopt", "xsavec",
1042 "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2",
1043 "fma", "movbe", "ept", "lzcnt", "popcnt", "hle", "rtm", "invpcid",
1044 "clflush", "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg",
1045 "uintr", "cldemote", "rdpru", "mcommit", "sev_es", "lwp", "fma4",
1046 "xop", "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a",
1047 "sse5", "snp", "invlpgb", "tlbsync", "svme" and "padlock". Note
1048 that rather than extending a basic instruction set, the extension
1049 mnemonics starting with "no" revoke the respective functionality.
1050 When the ".arch" directive is used with -march, the ".arch"
1052 directive will take precedent.
1053 -mtune=CPU
1055 This option specifies a processor to optimize for. When used in
1056 conjunction with the -march option, only instructions of the
1057 processor specified by the -march option will be generated.
1058 Valid CPU values are identical to the processor list of -march=CPU.
1060 -msse2avx
1062 This option specifies that the assembler should encode SSE
1063 instructions with VEX prefix.
1064 -muse-unaligned-vector-move
1066 This option specifies that the assembler should encode aligned
1067 vector move as unaligned vector move.
1068 -msse-check=none
1070 -msse-check=warning
1071 -msse-check=error
1072 These options control if the assembler should check SSE
1073 instructions. -msse-check=none will make the assembler not to
1074 check SSE instructions, which is the default. -msse-check=warning
1075 will make the assembler issue a warning for any SSE instruction.
1076 -msse-check=error will make the assembler issue an error for any
1077 SSE instruction.
1078 -mavxscalar=128
1080 -mavxscalar=256
1081 These options control how the assembler should encode scalar AVX
1082 instructions. -mavxscalar=128 will encode scalar AVX instructions
1083 with 128bit vector length, which is the default. -mavxscalar=256
1084 will encode scalar AVX instructions with 256bit vector length.
1085 WARNING: Don't use this for production code - due to CPU errata the
1087 resulting code may not work on certain models.
1088 -mvexwig=0
1090 -mvexwig=1
1091 These options control how the assembler should encode VEX.W-ignored
1092 (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX
1093 instructions with vex.w = 0, which is the default. -mvexwig=1 will
1094 encode WIG EVEX instructions with vex.w = 1.
1095 WARNING: Don't use this for production code - due to CPU errata the
1097 resulting code may not work on certain models.
1098 -mevexlig=128
1100 -mevexlig=256
1101 -mevexlig=512
1102 These options control how the assembler should encode length-
1103 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
1104 EVEX instructions with 128bit vector length, which is the default.
1105 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1106 with 256bit and 512bit vector length, respectively.
1107 -mevexwig=0
1109 -mevexwig=1
1110 These options control how the assembler should encode w-ignored
1111 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
1112 instructions with evex.w = 0, which is the default. -mevexwig=1
1113 will encode WIG EVEX instructions with evex.w = 1.
1114 -mmnemonic=att
1116 -mmnemonic=intel
1117 This option specifies instruction mnemonic for matching
1118 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
1119 will take precedent.
1120 -msyntax=att
1122 -msyntax=intel
1123 This option specifies instruction syntax when processing
1124 instructions. The ".att_syntax" and ".intel_syntax" directives
1125 will take precedent.
1126 -mnaked-reg
1128 This option specifies that registers don't require a % prefix. The
1129 ".att_syntax" and ".intel_syntax" directives will take precedent.
1130 -madd-bnd-prefix
1132 This option forces the assembler to add BND prefix to all branches,
1133 even if such prefix was not explicitly specified in the source
1134 code.
1135 -mno-shared
1137 On ELF target, the assembler normally optimizes out non-PLT
1138 relocations against defined non-weak global branch targets with
1139 default visibility. The -mshared option tells the assembler to
1140 generate code which may go into a shared library where all non-weak
1141 global branch targets with default visibility can be preempted.
1142 The resulting code is slightly bigger. This option only affects
1143 the handling of branch instructions.
1144 -mbig-obj
1146 On PE/COFF target this option forces the use of big object file
1147 format, which allows more than 32768 sections.
1148 -momit-lock-prefix=no
1150 -momit-lock-prefix=yes
1151 These options control how the assembler should encode lock prefix.
1152 This option is intended as a workaround for processors, that fail
1153 on lock prefix. This option can only be safely used with single-
1154 core, single-thread computers -momit-lock-prefix=yes will omit all
1155 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
1156 usual, which is the default.
1157 -mfence-as-lock-add=no
1159 -mfence-as-lock-add=yes
1160 These options control how the assembler should encode lfence,
1161 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
1162 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1163 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
1164 encode lfence, mfence and sfence as usual, which is the default.
1165 -mrelax-relocations=no
1167 -mrelax-relocations=yes
1168 These options control whether the assembler should generate relax
1169 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1170 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1171 -mrelax-relocations=yes will generate relax relocations.
1172 -mrelax-relocations=no will not generate relax relocations. The
1173 default can be controlled by a configure option
1174 --enable-x86-relax-relocations.
1175 -malign-branch-boundary=NUM
1177 This option controls how the assembler should align branches with
1178 segment prefixes or NOP. NUM must be a power of 2. It should be 0
1179 or no less than 16. Branches will be aligned within NUM byte
1180 boundary. -malign-branch-boundary=0, which is the default, doesn't
1181 align branches.
1182 -malign-branch=TYPE[+TYPE...]
1184 This option specifies types of branches to align. TYPE is
1185 combination of jcc, which aligns conditional jumps, fused, which
1186 aligns fused conditional jumps, jmp, which aligns unconditional
1187 jumps, call which aligns calls, ret, which aligns rets, indirect,
1188 which aligns indirect jumps and calls. The default is
1189 -malign-branch=jcc+fused+jmp.
1190 -malign-branch-prefix-size=NUM
1192 This option specifies the maximum number of prefixes on an
1193 instruction to align branches. NUM should be between 0 and 5. The
1194 default NUM is 5.
1195 -mbranches-within-32B-boundaries
1197 This option aligns conditional jumps, fused conditional jumps and
1198 unconditional jumps within 32 byte boundary with up to 5 segment
1199 prefixes on an instruction. It is equivalent to
1200 -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1201 -malign-branch-prefix-size=5. The default doesn't align branches.
1202 -mlfence-after-load=no
1204 -mlfence-after-load=yes
1205 These options control whether the assembler should generate lfence
1206 after load instructions. -mlfence-after-load=yes will generate
1207 lfence. -mlfence-after-load=no will not generate lfence, which is
1208 the default.
1209 -mlfence-before-indirect-branch=none
1211 -mlfence-before-indirect-branch=all
1212 -mlfence-before-indirect-branch=register
1213 -mlfence-before-indirect-branch=memory
1214 These options control whether the assembler should generate lfence
1215 before indirect near branch instructions.
1216 -mlfence-before-indirect-branch=all will generate lfence before
1217 indirect near branch via register and issue a warning before
1218 indirect near branch via memory. It also implicitly sets
1219 -mlfence-before-ret=shl when there's no explicit
1220 -mlfence-before-ret=. -mlfence-before-indirect-branch=register
1221 will generate lfence before indirect near branch via register.
1222 -mlfence-before-indirect-branch=memory will issue a warning before
1223 indirect near branch via memory.
1224 -mlfence-before-indirect-branch=none will not generate lfence nor
1225 issue warning, which is the default. Note that lfence won't be
1226 generated before indirect near branch via register with
1227 -mlfence-after-load=yes since lfence will be generated after
1228 loading branch target register.
1229 -mlfence-before-ret=none
1231 -mlfence-before-ret=shl
1232 -mlfence-before-ret=or
1233 -mlfence-before-ret=yes
1234 -mlfence-before-ret=not
1235 These options control whether the assembler should generate lfence
1236 before ret. -mlfence-before-ret=or will generate generate or
1237 instruction with lfence. -mlfence-before-ret=shl/yes will generate
1238 shl instruction with lfence. -mlfence-before-ret=not will generate
1239 not instruction with lfence. -mlfence-before-ret=none will not
1240 generate lfence, which is the default.
1241 -mx86-used-note=no
1243 -mx86-used-note=yes
1244 These options control whether the assembler should generate
1245 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1246 property notes. The default can be controlled by the
1247 --enable-x86-used-note configure option.
1248 -mevexrcig=rne
1250 -mevexrcig=rd
1251 -mevexrcig=ru
1252 -mevexrcig=rz
1253 These options control how the assembler should encode SAE-only EVEX
1254 instructions. -mevexrcig=rne will encode RC bits of EVEX
1255 instruction with 00, which is the default. -mevexrcig=rd,
1256 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1257 instructions with 01, 10 and 11 RC bits, respectively.
1258 -mamd64
1260 -mintel64
1261 This option specifies that the assembler should accept only AMD64
1262 or Intel64 ISA in 64-bit mode. The default is to accept common,
1263 Intel64 only and AMD64 ISAs.
1264 -O0 | -O | -O1 | -O2 | -Os
1266 Optimize instruction encoding with smaller instruction size. -O
1267 and -O1 encode 64-bit register load instructions with 64-bit
1268 immediate as 32-bit register load instructions with 31-bit or
1269 32-bits immediates, encode 64-bit register clearing instructions
1270 with 32-bit register clearing instructions, encode 256-bit/512-bit
1271 VEX/EVEX vector register clearing instructions with 128-bit VEX
1272 vector register clearing instructions, encode 128-bit/256-bit EVEX
1273 vector register load/store instructions with VEX vector register
1274 load/store instructions, and encode 128-bit/256-bit EVEX packed
1275 integer logical instructions with 128-bit/256-bit VEX packed
1276 integer logical.
1277 -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1279 vector register clearing instructions with 128-bit EVEX vector
1280 register clearing instructions. In 64-bit mode VEX encoded
1281 instructions with commutative source operands will also have their
1282 source operands swapped if this allows using the 2-byte VEX prefix
1283 form instead of the 3-byte one. Certain forms of AND as well as OR
1284 with the same (register) operand specified twice will also be
1285 changed to TEST.
1286 -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1288 64-bit register tests with immediate as 8-bit register test with
1289 immediate. -O0 turns off this optimization.
1290 The following options are available when as is configured for the
1292 Ubicom IP2K series.
1293 -mip2022ext
1295 Specifies that the extended IP2022 instructions are allowed.
1296 -mip2022
1298 Restores the default behaviour, which restricts the permitted
1299 instructions to just the basic IP2022 ones.
1300 The following options are available when as is configured for the
1302 Renesas M32C and M16C processors.
1303 -m32c
1305 Assemble M32C instructions.
1306 -m16c
1308 Assemble M16C instructions (the default).
1309 -relax
1311 Enable support for link-time relaxations.
1312 -h-tick-hex
1314 Support H'00 style hex constants in addition to 0x00 style.
1315 The following options are available when as is configured for the
1317 Renesas M32R (formerly Mitsubishi M32R) series.
1318 --m32rx
1320 Specify which processor in the M32R family is the target. The
1321 default is normally the M32R, but this option changes it to the
1322 M32RX.
1323 --warn-explicit-parallel-conflicts or --Wp
1325 Produce warning messages when questionable parallel constructs are
1326 encountered.
1327 --no-warn-explicit-parallel-conflicts or --Wnp
1329 Do not produce warning messages when questionable parallel
1330 constructs are encountered.
1331 The following options are available when as is configured for the
1333 Motorola 68000 series.
1334 -l Shorten references to undefined symbols, to one word instead of
1336 two.
1337 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1339 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1340 | -m68333 | -m68340 | -mcpu32 | -m5200
1341 Specify what processor in the 68000 family is the target. The
1342 default is normally the 68020, but this can be changed at
1343 configuration time.
1344 -m68881 | -m68882 | -mno-68881 | -mno-68882
1346 The target machine does (or does not) have a floating-point
1347 coprocessor. The default is to assume a coprocessor for 68020,
1348 68030, and cpu32. Although the basic 68000 is not compatible with
1349 the 68881, a combination of the two can be specified, since it's
1350 possible to do emulation of the coprocessor instructions with the
1351 main processor.
1352 -m68851 | -mno-68851
1354 The target machine does (or does not) have a memory-management unit
1355 coprocessor. The default is to assume an MMU for 68020 and up.
1356 The following options are available when as is configured for an Altera
1358 Nios II processor.
1359 -relax-section
1361 Replace identified out-of-range branches with PC-relative "jmp"
1362 sequences when possible. The generated code sequences are suitable
1363 for use in position-independent code, but there is a practical
1364 limit on the extended branch range because of the length of the
1365 sequences. This option is the default.
1366 -relax-all
1368 Replace branch instructions not determinable to be in range and all
1369 call instructions with "jmp" and "callr" sequences (respectively).
1370 This option generates absolute relocations against the target
1371 symbols and is not appropriate for position-independent code.
1372 -no-relax
1374 Do not replace any branches or calls.
1375 -EB Generate big-endian output.
1377 -EL Generate little-endian output. This is the default.
1379 -march=architecture
1381 This option specifies the target architecture. The assembler
1382 issues an error message if an attempt is made to assemble an
1383 instruction which will not execute on the target architecture. The
1384 following architecture names are recognized: "r1", "r2". The
1385 default is "r1".
1386 The following options are available when as is configured for a PRU
1388 processor.
1389 -mlink-relax
1391 Assume that LD would optimize LDI32 instructions by checking the
1392 upper 16 bits of the expression. If they are all zeros, then LD
1393 would shorten the LDI32 instruction to a single LDI. In such case
1394 "as" will output DIFF relocations for diff expressions.
1395 -mno-link-relax
1397 Assume that LD would not optimize LDI32 instructions. As a
1398 consequence, DIFF relocations will not be emitted.
1399 -mno-warn-regname-label
1401 Do not warn if a label name matches a register name. Usually
1402 assembler programmers will want this warning to be emitted. C
1403 compilers may want to turn this off.
1404 The following options are available when as is configured for a MIPS
1406 processor.
1407 -G num
1409 This option sets the largest size of an object that can be
1410 referenced implicitly with the "gp" register. It is only accepted
1411 for targets that use ECOFF format, such as a DECstation running
1412 Ultrix. The default value is 8.
1413 -EB Generate "big endian" format output.
1415 -EL Generate "little endian" format output.
1417 -mips1
1419 -mips2
1420 -mips3
1421 -mips4
1422 -mips5
1423 -mips32
1424 -mips32r2
1425 -mips32r3
1426 -mips32r5
1427 -mips32r6
1428 -mips64
1429 -mips64r2
1430 -mips64r3
1431 -mips64r5
1432 -mips64r6
1433 Generate code for a particular MIPS Instruction Set Architecture
1434 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1435 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1436 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1437 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1438 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1439 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1440 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1441 Release 6 ISA processors, respectively.
1442 -march=cpu
1444 Generate code for a particular MIPS CPU.
1445 -mtune=cpu
1447 Schedule and tune for a particular MIPS CPU.
1448 -mfix7000
1450 -mno-fix7000
1451 Cause nops to be inserted if the read of the destination register
1452 of an mfhi or mflo instruction occurs in the following two
1453 instructions.
1454 -mfix-rm7000
1456 -mno-fix-rm7000
1457 Cause nops to be inserted if a dmult or dmultu instruction is
1458 followed by a load instruction.
1459 -mfix-r5900
1461 -mno-fix-r5900
1462 Do not attempt to schedule the preceding instruction into the delay
1463 slot of a branch instruction placed at the end of a short loop of
1464 six instructions or fewer and always schedule a "nop" instruction
1465 there instead. The short loop bug under certain conditions causes
1466 loops to execute only once or twice, due to a hardware bug in the
1467 R5900 chip.
1468 -mdebug
1470 -no-mdebug
1471 Cause stabs-style debugging output to go into an ECOFF-style
1472 .mdebug section instead of the standard ELF .stabs sections.
1473 -mpdr
1475 -mno-pdr
1476 Control generation of ".pdr" sections.
1477 -mgp32
1479 -mfp32
1480 The register sizes are normally inferred from the ISA and ABI, but
1481 these flags force a certain group of registers to be treated as 32
1482 bits wide at all times. -mgp32 controls the size of general-
1483 purpose registers and -mfp32 controls the size of floating-point
1484 registers.
1485 -mgp64
1487 -mfp64
1488 The register sizes are normally inferred from the ISA and ABI, but
1489 these flags force a certain group of registers to be treated as 64
1490 bits wide at all times. -mgp64 controls the size of general-
1491 purpose registers and -mfp64 controls the size of floating-point
1492 registers.
1493 -mfpxx
1495 The register sizes are normally inferred from the ISA and ABI, but
1496 using this flag in combination with -mabi=32 enables an ABI variant
1497 which will operate correctly with floating-point registers which
1498 are 32 or 64 bits wide.
1499 -modd-spreg
1501 -mno-odd-spreg
1502 Enable use of floating-point operations on odd-numbered single-
1503 precision registers when supported by the ISA. -mfpxx implies
1504 -mno-odd-spreg, otherwise the default is -modd-spreg.
1505 -mips16
1507 -no-mips16
1508 Generate code for the MIPS 16 processor. This is equivalent to
1509 putting ".module mips16" at the start of the assembly file.
1510 -no-mips16 turns off this option.
1511 -mmips16e2
1513 -mno-mips16e2
1514 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1515 equivalent to putting ".module mips16e2" at the start of the
1516 assembly file. -mno-mips16e2 turns off this option.
1517 -mmicromips
1519 -mno-micromips
1520 Generate code for the microMIPS processor. This is equivalent to
1521 putting ".module micromips" at the start of the assembly file.
1522 -mno-micromips turns off this option. This is equivalent to
1523 putting ".module nomicromips" at the start of the assembly file.
1524 -msmartmips
1526 -mno-smartmips
1527 Enables the SmartMIPS extension to the MIPS32 instruction set.
1528 This is equivalent to putting ".module smartmips" at the start of
1529 the assembly file. -mno-smartmips turns off this option.
1530 -mips3d
1532 -no-mips3d
1533 Generate code for the MIPS-3D Application Specific Extension. This
1534 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1535 turns off this option.
1536 -mdmx
1538 -no-mdmx
1539 Generate code for the MDMX Application Specific Extension. This
1540 tells the assembler to accept MDMX instructions. -no-mdmx turns
1541 off this option.
1542 -mdsp
1544 -mno-dsp
1545 Generate code for the DSP Release 1 Application Specific Extension.
1546 This tells the assembler to accept DSP Release 1 instructions.
1547 -mno-dsp turns off this option.
1548 -mdspr2
1550 -mno-dspr2
1551 Generate code for the DSP Release 2 Application Specific Extension.
1552 This option implies -mdsp. This tells the assembler to accept DSP
1553 Release 2 instructions. -mno-dspr2 turns off this option.
1554 -mdspr3
1556 -mno-dspr3
1557 Generate code for the DSP Release 3 Application Specific Extension.
1558 This option implies -mdsp and -mdspr2. This tells the assembler to
1559 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1560 option.
1561 -mmsa
1563 -mno-msa
1564 Generate code for the MIPS SIMD Architecture Extension. This tells
1565 the assembler to accept MSA instructions. -mno-msa turns off this
1566 option.
1567 -mxpa
1569 -mno-xpa
1570 Generate code for the MIPS eXtended Physical Address (XPA)
1571 Extension. This tells the assembler to accept XPA instructions.
1572 -mno-xpa turns off this option.
1573 -mmt
1575 -mno-mt
1576 Generate code for the MT Application Specific Extension. This
1577 tells the assembler to accept MT instructions. -mno-mt turns off
1578 this option.
1579 -mmcu
1581 -mno-mcu
1582 Generate code for the MCU Application Specific Extension. This
1583 tells the assembler to accept MCU instructions. -mno-mcu turns off
1584 this option.
1585 -mcrc
1587 -mno-crc
1588 Generate code for the MIPS cyclic redundancy check (CRC)
1589 Application Specific Extension. This tells the assembler to accept
1590 CRC instructions. -mno-crc turns off this option.
1591 -mginv
1593 -mno-ginv
1594 Generate code for the Global INValidate (GINV) Application Specific
1595 Extension. This tells the assembler to accept GINV instructions.
1596 -mno-ginv turns off this option.
1597 -mloongson-mmi
1599 -mno-loongson-mmi
1600 Generate code for the Loongson MultiMedia extensions Instructions
1601 (MMI) Application Specific Extension. This tells the assembler to
1602 accept MMI instructions. -mno-loongson-mmi turns off this option.
1603 -mloongson-cam
1605 -mno-loongson-cam
1606 Generate code for the Loongson Content Address Memory (CAM)
1607 instructions. This tells the assembler to accept Loongson CAM
1608 instructions. -mno-loongson-cam turns off this option.
1609 -mloongson-ext
1611 -mno-loongson-ext
1612 Generate code for the Loongson EXTensions (EXT) instructions. This
1613 tells the assembler to accept Loongson EXT instructions.
1614 -mno-loongson-ext turns off this option.
1615 -mloongson-ext2
1617 -mno-loongson-ext2
1618 Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1619 This option implies -mloongson-ext. This tells the assembler to
1620 accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off
1621 this option.
1622 -minsn32
1624 -mno-insn32
1625 Only use 32-bit instruction encodings when generating code for the
1626 microMIPS processor. This option inhibits the use of any 16-bit
1627 instructions. This is equivalent to putting ".set insn32" at the
1628 start of the assembly file. -mno-insn32 turns off this option.
1629 This is equivalent to putting ".set noinsn32" at the start of the
1630 assembly file. By default -mno-insn32 is selected, allowing all
1631 instructions to be used.
1632 --construct-floats
1634 --no-construct-floats
1635 The --no-construct-floats option disables the construction of
1636 double width floating point constants by loading the two halves of
1637 the value into the two single width floating point registers that
1638 make up the double width register. By default --construct-floats
1639 is selected, allowing construction of these floating point
1640 constants.
1641 --relax-branch
1643 --no-relax-branch
1644 The --relax-branch option enables the relaxation of out-of-range
1645 branches. By default --no-relax-branch is selected, causing any
1646 out-of-range branches to produce an error.
1647 -mignore-branch-isa
1649 -mno-ignore-branch-isa
1650 Ignore branch checks for invalid transitions between ISA modes.
1651 The semantics of branches does not provide for an ISA mode switch,
1652 so in most cases the ISA mode a branch has been encoded for has to
1653 be the same as the ISA mode of the branch's target label.
1654 Therefore GAS has checks implemented that verify in branch assembly
1655 that the two ISA modes match. -mignore-branch-isa disables these
1656 checks. By default -mno-ignore-branch-isa is selected, causing any
1657 invalid branch requiring a transition between ISA modes to produce
1658 an error.
1659 -mnan=encoding
1661 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1662 (-mnan=legacy) NaN encoding format. The latter is the default.
1663 --emulation=name
1665 This option was formerly used to switch between ELF and ECOFF
1666 output on targets like IRIX 5 that supported both. MIPS ECOFF
1667 support was removed in GAS 2.24, so the option now serves little
1668 purpose. It is retained for backwards compatibility.
1669 The available configuration names are: mipself, mipslelf and
1671 mipsbelf. Choosing mipself now has no effect, since the output is
1672 always ELF. mipslelf and mipsbelf select little- and big-endian
1673 output respectively, but -EL and -EB are now the preferred options
1674 instead.
1675 -nocpp
1677 as ignores this option. It is accepted for compatibility with the
1678 native tools.
1679 --trap
1681 --no-trap
1682 --break
1683 --no-break
1684 Control how to deal with multiplication overflow and division by
1685 zero. --trap or --no-break (which are synonyms) take a trap
1686 exception (and only work for Instruction Set Architecture level 2
1687 and higher); --break or --no-trap (also synonyms, and the default)
1688 take a break exception.
1689 -n When this option is used, as will issue a warning every time it
1691 generates a nop instruction from a macro.
1692 The following options are available when as is configured for a
1694 LoongArch processor.
1695 -fpic
1697 -fPIC
1698 Generate position-independent code
1699 -fno-pic
1701 Don't generate position-independent code (default)
1702 The following options are available when as is configured for a Meta
1704 processor.
1705 "-mcpu=metac11"
1707 Generate code for Meta 1.1.
1708 "-mcpu=metac12"
1710 Generate code for Meta 1.2.
1711 "-mcpu=metac21"
1713 Generate code for Meta 2.1.
1714 "-mfpu=metac21"
1716 Allow code to use FPU hardware of Meta 2.1.
1717 See the info pages for documentation of the MMIX-specific options.
1719 The following options are available when as is configured for a NDS32
1721 processor.
1722 "-O1"
1724 Optimize for performance.
1725 "-Os"
1727 Optimize for space.
1728 "-EL"
1730 Produce little endian data output.
1731 "-EB"
1733 Produce little endian data output.
1734 "-mpic"
1736 Generate PIC.
1737 "-mno-fp-as-gp-relax"
1739 Suppress fp-as-gp relaxation for this file.
1740 "-mb2bb-relax"
1742 Back-to-back branch optimization.
1743 "-mno-all-relax"
1745 Suppress all relaxation for this file.
1746 "-march=<arch name>"
1748 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1749 v3f, v3s, v2, v2j, v2f, v2s.
1750 "-mbaseline=<baseline>"
1752 Assemble for baseline <baseline> which could be v2, v3, v3m.
1753 "-mfpu-freg=FREG"
1755 Specify a FPU configuration.
1756 "0 8 SP / 4 DP registers"
1758 "1 16 SP / 8 DP registers"
1759 "2 32 SP / 16 DP registers"
1760 "3 32 SP / 32 DP registers"
1761 "-mabi=abi"
1762 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1763 "-m[no-]mac"
1765 Enable/Disable Multiply instructions support.
1766 "-m[no-]div"
1768 Enable/Disable Divide instructions support.
1769 "-m[no-]16bit-ext"
1771 Enable/Disable 16-bit extension
1772 "-m[no-]dx-regs"
1774 Enable/Disable d0/d1 registers
1775 "-m[no-]perf-ext"
1777 Enable/Disable Performance extension
1778 "-m[no-]perf2-ext"
1780 Enable/Disable Performance extension 2
1781 "-m[no-]string-ext"
1783 Enable/Disable String extension
1784 "-m[no-]reduced-regs"
1786 Enable/Disable Reduced Register configuration (GPR16) option
1787 "-m[no-]audio-isa-ext"
1789 Enable/Disable AUDIO ISA extension
1790 "-m[no-]fpu-sp-ext"
1792 Enable/Disable FPU SP extension
1793 "-m[no-]fpu-dp-ext"
1795 Enable/Disable FPU DP extension
1796 "-m[no-]fpu-fma"
1798 Enable/Disable FPU fused-multiply-add instructions
1799 "-mall-ext"
1801 Turn on all extensions and instructions support
1802 The following options are available when as is configured for a PowerPC
1804 processor.
1805 -a32
1807 Generate ELF32 or XCOFF32.
1808 -a64
1810 Generate ELF64 or XCOFF64.
1811 -K PIC
1813 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1814 -mpwrx | -mpwr2
1816 Generate code for POWER/2 (RIOS2).
1817 -mpwr
1819 Generate code for POWER (RIOS1)
1820 -m601
1822 Generate code for PowerPC 601.
1823 -mppc, -mppc32, -m603, -m604
1825 Generate code for PowerPC 603/604.
1826 -m403, -m405
1828 Generate code for PowerPC 403/405.
1829 -m440
1831 Generate code for PowerPC 440. BookE and some 405 instructions.
1832 -m464
1834 Generate code for PowerPC 464.
1835 -m476
1837 Generate code for PowerPC 476.
1838 -m7400, -m7410, -m7450, -m7455
1840 Generate code for PowerPC 7400/7410/7450/7455.
1841 -m750cl, -mgekko, -mbroadway
1843 Generate code for PowerPC 750CL/Gekko/Broadway.
1844 -m821, -m850, -m860
1846 Generate code for PowerPC 821/850/860.
1847 -mppc64, -m620
1849 Generate code for PowerPC 620/625/630.
1850 -me500, -me500x2
1852 Generate code for Motorola e500 core complex.
1853 -me500mc
1855 Generate code for Freescale e500mc core complex.
1856 -me500mc64
1858 Generate code for Freescale e500mc64 core complex.
1859 -me5500
1861 Generate code for Freescale e5500 core complex.
1862 -me6500
1864 Generate code for Freescale e6500 core complex.
1865 -mspe
1867 Generate code for Motorola SPE instructions.
1868 -mspe2
1870 Generate code for Freescale SPE2 instructions.
1871 -mtitan
1873 Generate code for AppliedMicro Titan core complex.
1874 -mppc64bridge
1876 Generate code for PowerPC 64, including bridge insns.
1877 -mbooke
1879 Generate code for 32-bit BookE.
1880 -ma2
1882 Generate code for A2 architecture.
1883 -me300
1885 Generate code for PowerPC e300 family.
1886 -maltivec
1888 Generate code for processors with AltiVec instructions.
1889 -mvle
1891 Generate code for Freescale PowerPC VLE instructions.
1892 -mvsx
1894 Generate code for processors with Vector-Scalar (VSX) instructions.
1895 -mhtm
1897 Generate code for processors with Hardware Transactional Memory
1898 instructions.
1899 -mpower4, -mpwr4
1901 Generate code for Power4 architecture.
1902 -mpower5, -mpwr5, -mpwr5x
1904 Generate code for Power5 architecture.
1905 -mpower6, -mpwr6
1907 Generate code for Power6 architecture.
1908 -mpower7, -mpwr7
1910 Generate code for Power7 architecture.
1911 -mpower8, -mpwr8
1913 Generate code for Power8 architecture.
1914 -mpower9, -mpwr9
1916 Generate code for Power9 architecture.
1917 -mpower10, -mpwr10
1919 Generate code for Power10 architecture.
1920 -mcell
1922 -mcell
1923 Generate code for Cell Broadband Engine architecture.
1924 -mcom
1926 Generate code Power/PowerPC common instructions.
1927 -many
1929 Generate code for any architecture (PWR/PWRX/PPC).
1930 -mregnames
1932 Allow symbolic names for registers.
1933 -mno-regnames
1935 Do not allow symbolic names for registers.
1936 -mrelocatable
1938 Support for GCC's -mrelocatable option.
1939 -mrelocatable-lib
1941 Support for GCC's -mrelocatable-lib option.
1942 -memb
1944 Set PPC_EMB bit in ELF flags.
1945 -mlittle, -mlittle-endian, -le
1947 Generate code for a little endian machine.
1948 -mbig, -mbig-endian, -be
1950 Generate code for a big endian machine.
1951 -msolaris
1953 Generate code for Solaris.
1954 -mno-solaris
1956 Do not generate code for Solaris.
1957 -nops=count
1959 If an alignment directive inserts more than count nops, put a
1960 branch at the beginning to skip execution of the nops.
1961 The following options are available when as is configured for a RISC-V
1963 processor.
1964 -fpic
1966 -fPIC
1967 Generate position-independent code
1968 -fno-pic
1970 Don't generate position-independent code (default)
1971 -march=ISA
1973 Select the base isa, as specified by ISA. For example
1974 -march=rv32ima. If this option and the architecture attributes
1975 aren't set, then assembler will check the default configure setting
1976 --with-arch=ISA.
1977 -misa-spec=ISAspec
1979 Select the default isa spec version. If the version of ISA isn't
1980 set by -march, then assembler helps to set the version according to
1981 the default chosen spec. If this option isn't set, then assembler
1982 will check the default configure setting --with-isa-spec=ISAspec.
1983 -mpriv-spec=PRIVspec
1985 Select the privileged spec version. We can decide whether the CSR
1986 is valid or not according to the chosen spec. If this option and
1987 the privilege attributes aren't set, then assembler will check the
1988 default configure setting --with-priv-spec=PRIVspec.
1989 -mabi=ABI
1991 Selects the ABI, which is either "ilp32" or "lp64", optionally
1992 followed by "f", "d", or "q" to indicate single-precision, double-
1993 precision, or quad-precision floating-point calling convention, or
1994 none to indicate the soft-float calling convention. Also, "ilp32"
1995 can optionally be followed by "e" to indicate the RVE ABI, which is
1996 always soft-float.
1997 -mrelax
1999 Take advantage of linker relaxations to reduce the number of
2000 instructions required to materialize symbol addresses. (default)
2001 -mno-relax
2003 Don't do linker relaxations.
2004 -march-attr
2006 Generate the default contents for the riscv elf attribute section
2007 if the .attribute directives are not set. This section is used to
2008 record the information that a linker or runtime loader needs to
2009 check compatibility. This information includes ISA string, stack
2010 alignment requirement, unaligned memory accesses, and the major,
2011 minor and revision version of privileged specification.
2012 -mno-arch-attr
2014 Don't generate the default riscv elf attribute section if the
2015 .attribute directives are not set.
2016 -mcsr-check
2018 Enable the CSR checking for the ISA-dependent CRS and the read-only
2019 CSR. The ISA-dependent CSR are only valid when the specific ISA is
2020 set. The read-only CSR can not be written by the CSR instructions.
2021 -mno-csr-check
2023 Don't do CSR checking.
2024 -mlittle-endian
2026 Generate code for a little endian machine.
2027 -mbig-endian
2029 Generate code for a big endian machine.
2030 See the info pages for documentation of the RX-specific options.
2032 The following options are available when as is configured for the s390
2034 processor family.
2035 -m31
2037 -m64
2038 Select the word size, either 31/32 bits or 64 bits.
2039 -mesa
2041 -mzarch
2042 Select the architecture mode, either the Enterprise System
2043 Architecture (esa) or the z/Architecture mode (zarch).
2044 -march=processor
2046 Specify which s390 processor variant is the target, g5 (or arch3),
2047 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2048 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2049 z14 (or arch12), z15 (or arch13), or z16 (or arch14).
2050 -mregnames
2052 -mno-regnames
2053 Allow or disallow symbolic names for registers.
2054 -mwarn-areg-zero
2056 Warn whenever the operand for a base or index register has been
2057 specified but evaluates to zero.
2058 The following options are available when as is configured for a
2060 TMS320C6000 processor.
2061 -march=arch
2063 Enable (only) instructions from architecture arch. By default, all
2064 instructions are permitted.
2065 The following values of arch are accepted: "c62x", "c64x", "c64x+",
2067 "c67x", "c67x+", "c674x".
2068 -mdsbt
2070 -mno-dsbt
2071 The -mdsbt option causes the assembler to generate the
2072 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2073 code is using DSBT addressing. The -mno-dsbt option, the default,
2074 causes the tag to have a value of 0, indicating that the code does
2075 not use DSBT addressing. The linker will emit a warning if objects
2076 of different type (DSBT and non-DSBT) are linked together.
2077 -mpid=no
2079 -mpid=near
2080 -mpid=far
2081 The -mpid= option causes the assembler to generate the
2082 "Tag_ABI_PID" attribute with a value indicating the form of data
2083 addressing used by the code. -mpid=no, the default, indicates
2084 position-dependent data addressing, -mpid=near indicates position-
2085 independent addressing with GOT accesses using near DP addressing,
2086 and -mpid=far indicates position-independent addressing with GOT
2087 accesses using far DP addressing. The linker will emit a warning
2088 if objects built with different settings of this option are linked
2089 together.
2090 -mpic
2092 -mno-pic
2093 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2094 attribute with a value of 1, indicating that the code is using
2095 position-independent code addressing, The "-mno-pic" option, the
2096 default, causes the tag to have a value of 0, indicating position-
2097 dependent code addressing. The linker will emit a warning if
2098 objects of different type (position-dependent and position-
2099 independent) are linked together.
2100 -mbig-endian
2102 -mlittle-endian
2103 Generate code for the specified endianness. The default is little-
2104 endian.
2105 The following options are available when as is configured for a TILE-Gx
2107 processor.
2108 -m32 | -m64
2110 Select the word size, either 32 bits or 64 bits.
2111 -EB | -EL
2113 Select the endianness, either big-endian (-EB) or little-endian
2114 (-EL).
2115 The following option is available when as is configured for a Visium
2117 processor.
2118 -mtune=arch
2120 This option specifies the target architecture. If an attempt is
2121 made to assemble an instruction that will not execute on the target
2122 architecture, the assembler will issue an error message.
2123 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2125 The following options are available when as is configured for an Xtensa
2127 processor.
2128 --text-section-literals | --no-text-section-literals
2130 Control the treatment of literal pools. The default is
2131 --no-text-section-literals, which places literals in separate
2132 sections in the output file. This allows the literal pool to be
2133 placed in a data RAM/ROM. With --text-section-literals, the
2134 literals are interspersed in the text section in order to keep them
2135 as close as possible to their references. This may be necessary
2136 for large assembly files, where the literals would otherwise be out
2137 of range of the "L32R" instructions in the text section. Literals
2138 are grouped into pools following ".literal_position" directives or
2139 preceding "ENTRY" instructions. These options only affect literals
2140 referenced via PC-relative "L32R" instructions; literals for
2141 absolute mode "L32R" instructions are handled separately.
2142 --auto-litpools | --no-auto-litpools
2144 Control the treatment of literal pools. The default is
2145 --no-auto-litpools, which in the absence of --text-section-literals
2146 places literals in separate sections in the output file. This
2147 allows the literal pool to be placed in a data RAM/ROM. With
2148 --auto-litpools, the literals are interspersed in the text section
2149 in order to keep them as close as possible to their references,
2150 explicit ".literal_position" directives are not required. This may
2151 be necessary for very large functions, where single literal pool at
2152 the beginning of the function may not be reachable by "L32R"
2153 instructions at the end. These options only affect literals
2154 referenced via PC-relative "L32R" instructions; literals for
2155 absolute mode "L32R" instructions are handled separately. When
2156 used together with --text-section-literals, --auto-litpools takes
2157 precedence.
2158 --absolute-literals | --no-absolute-literals
2160 Indicate to the assembler whether "L32R" instructions use absolute
2161 or PC-relative addressing. If the processor includes the absolute
2162 addressing option, the default is to use absolute "L32R"
2163 relocations. Otherwise, only the PC-relative "L32R" relocations
2164 can be used.
2165 --target-align | --no-target-align
2167 Enable or disable automatic alignment to reduce branch penalties at
2168 some expense in code size. This optimization is enabled by
2169 default. Note that the assembler will always align instructions
2170 like "LOOP" that have fixed alignment requirements.
2171 --longcalls | --no-longcalls
2173 Enable or disable transformation of call instructions to allow
2174 calls across a greater range of addresses. This option should be
2175 used when call targets can potentially be out of range. It may
2176 degrade both code size and performance, but the linker can
2177 generally optimize away the unnecessary overhead when a call ends
2178 up within range. The default is --no-longcalls.
2179 --transform | --no-transform
2181 Enable or disable all assembler transformations of Xtensa
2182 instructions, including both relaxation and optimization. The
2183 default is --transform; --no-transform should only be used in the
2184 rare cases when the instructions must be exactly as specified in
2185 the assembly source. Using --no-transform causes out of range
2186 instruction operands to be errors.
2187 --rename-section oldname=newname
2189 Rename the oldname section to newname. This option can be used
2190 multiple times to rename multiple sections.
2191 --trampolines | --no-trampolines
2193 Enable or disable transformation of jump instructions to allow
2194 jumps across a greater range of addresses. This option should be
2195 used when jump targets can potentially be out of range. In the
2196 absence of such jumps this option does not affect code size or
2197 performance. The default is --trampolines.
2198 --abi-windowed | --abi-call0
2200 Choose ABI tag written to the ".xtensa.info" section. ABI tag
2201 indicates ABI of the assembly code. A warning is issued by the
2202 linker on an attempt to link object files with inconsistent ABI
2203 tags. Default ABI is chosen by the Xtensa core configuration.
2204 The following options are available when as is configured for an Z80
2206 processor.
2207 @chapter Z80 Dependent Features
2209 Command-line Options
2211 -march=CPU[-EXT...][+EXT...]
2212 This option specifies the target processor. The assembler will
2213 issue an error message if an attempt is made to assemble an
2214 instruction which will not execute on the target processor. The
2215 following processor names are recognized: "z80", "z180", "ez80",
2216 "gbz80", "z80n", "r800". In addition to the basic instruction set,
2217 the assembler can be told to accept some extention mnemonics. For
2218 example, "-march=z180+sli+infc" extends z180 with SLI instructions
2219 and IN F,(C). The following extentions are currently supported:
2220 "full" (all known instructions), "adl" (ADL CPU mode by default,
2221 eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2222 (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2223 "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2224 "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2225 (C),0). Note that rather than extending a basic instruction set,
2226 the extention mnemonics starting with "-" revoke the respective
2227 functionality: "-march=z80-full+xyhl" first removes all default
2228 extentions and adds support for index registers halves only.
2229 If this option is not specified then "-march=z80+xyhl+infc" is
2231 assumed.
2232 -local-prefix=prefix
2234 Mark all labels with specified prefix as local. But such label can
2235 be marked global explicitly in the code. This option do not change
2236 default local label prefix ".L", it is just adds new one.
2237 -colonless
2239 Accept colonless labels. All symbols at line begin are treated as
2240 labels.
2241 -sdcc
2243 Accept assembler code produced by SDCC.
2244 -fp-s=FORMAT
2246 Single precision floating point numbers format. Default: ieee754
2247 (32 bit).
2248 -fp-d=FORMAT
2250 Double precision floating point numbers format. Default: ieee754
2251 (64 bit).
2252
2254 gcc(1), ld(1), and the Info entries for binutils and ld.
2255
2257 Copyright (c) 1991-2022 Free Software Foundation, Inc.
2258 Permission is granted to copy, distribute and/or modify this document
2260 under the terms of the GNU Free Documentation License, Version 1.3 or
2261 any later version published by the Free Software Foundation; with no
2262 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2263 Texts. A copy of the license is included in the section entitled "GNU
2264 Free Documentation License".
2265binutils-2.39 2023-10-30 AS(1)