1GBZ80(7) BSD Miscellaneous Information Manual GBZ80(7)
2
4 gbz80 — CPU opcode reference
5
7 This is the list of opcodes supported by rgbasm(1), including a short
8 description, the number of bytes needed to encode them and the number of
9 CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
10 them.
11 Note: All arithmetic/logic operations that use register A as destination
13 can omit the destination as it is assumed it's register A. The following
14 two lines have the same effect:
15 OR A,B
17 OR B
18
20 List of abbreviations used in this document.
21 r8 Any of the 8-bit registers (A, B, C, D, E, H, L).
23 r16 Any of the general-purpose 16-bit registers (BC, DE, HL).
25 n8 8-bit integer constant.
27 n16 16-bit integer constant.
29 e8 8-bit offset (-128 to 127).
31 u3 3-bit unsigned integer constant (0 to 7).
33 cc Condition codes:
35 Z: Execute if Z is set.
36 NZ: Execute if Z is not set.
37 C: Execute if C is set.
38 NC: Execute if C is not set.
39 vec One of the RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28,
41 0x30 and 0x38).
42
44 8-bit Arithmetic and Logic Instructions
45 ADC A,r8
46 ADC A,[HL]
47 ADC A,n8
48 ADD A,r8
49 ADD A,[HL]
50 ADD A,n8
51 AND A,r8
52 AND A,[HL]
53 AND A,n8
54 CP A,r8
55 CP A,[HL]
56 CP A,n8
57 DEC r8
58 DEC [HL]
59 INC r8
60 INC [HL]
61 OR A,r8
62 OR A,[HL]
63 OR A,n8
64 SBC A,r8
65 SBC A,[HL]
66 SBC A,n8
67 SUB A,r8
68 SUB A,[HL]
69 SUB A,n8
70 XOR A,r8
71 XOR A,[HL]
72 XOR A,n8
73 16-bit Arithmetic Instructions
75 ADD HL,r16
76 DEC r16
77 INC r16
78 Bit Operations Instructions
80 BIT u3,r8
81 BIT u3,[HL]
82 RES u3,r8
83 RES u3,[HL]
84 SET u3,r8
85 SET u3,[HL]
86 SWAP r8
87 SWAP [HL]
88 Bit Shift Instructions
90 RL r8
91 RL [HL]
92 RLA
93 RLC r8
94 RLC [HL]
95 RLCA
96 RR r8
97 RR [HL]
98 RRA
99 RRC r8
100 RRC [HL]
101 RRCA
102 SLA r8
103 SLA [HL]
104 SRA r8
105 SRA [HL]
106 SRL r8
107 SRL [HL]
108 Load Instructions
110 LD r8,r8
111 LD r8,n8
112 LD r16,n16
113 LD [HL],r8
114 LD [HL],n8
115 LD r8,[HL]
116 LD [r16],A
117 LD [n16],A
118 LD [$FF00+n8],A
119 LD [$FF00+C],A
120 LD A,[r16]
121 LD A,[n16]
122 LD A,[$FF00+n8]
123 LD A,[$FF00+C]
124 LD [HL+],A
125 LD [HL-],A
126 LD A,[HL+]
127 LD A,[HL-]
128 Jumps and Subroutines
130 CALL n16
131 CALL cc,n16
132 JP HL
133 JP n16
134 JP cc,n16
135 JR e8
136 JR cc,e8
137 RET cc
138 RET
139 RETI
140 RST vec
141 Stack Operations Instructions
143 ADD HL,SP
144 ADD SP,e8
145 DEC SP
146 INC SP
147 LD SP,n16
148 LD [n16],SP
149 LD HL,SP+e8
150 LD SP,HL
151 POP AF
152 POP r16
153 PUSH AF
154 PUSH r16
155 Miscelaneous Instructions
157 CCF
158 CPL
159 DAA
160 DI
161 EI
162 HALT
163 NOP
164 SCF
165 STOP
166
168 ADC A,r8
169 Add the value in r8 plus the carry flag to A.
170 Cycles: 1
172 Bytes: 1
174 Flags:
176 · Z: Set if result is 0.
177 · N: 0
178 · H: Set if overflow from bit 3.
179 · C: Set if overflow from bit 7.
180 ADC A,[HL]
182 Add the value pointed by HL plus the carry flag to A.
183 Cycles: 2
185 Bytes: 1
187 Flags: See ADC A,r8
189 ADC A,n8
191 Add the value n8 plus the carry flag to A.
192 Cycles: 2
194 Bytes: 2
196 Flags: See ADC A,r8
198 ADD A,r8
200 Add the value in r8 to A.
201 Cycles: 1
203 Bytes: 1
205 Flags:
207 · Z: Set if result is 0.
208 · N: 0
209 · H: Set if overflow from bit 3.
210 · C: Set if overflow from bit 7.
211 ADD A,[HL]
213 Add the value pointed by HL to A.
214 Cycles: 2
216 Bytes: 1
218 Flags: See ADD A,r8
220 ADD A,n8
222 Add the value n8 to A.
223 Cycles: 2
225 Bytes: 2
227 Flags: See ADD A,r8
229 ADD HL,r16
231 Add the value in r16 to HL.
232 Cycles: 2
234 Bytes: 1
236 Flags:
238 · N: 0
239 · H: Set if overflow from bit 11.
240 · C: Set if overflow from bit 15.
241 ADD HL,SP
243 Add the value in SP to HL.
244 Cycles: 2
246 Bytes: 1
248 Flags: See ADD HL,r16
250 ADD SP,e8
252 Add the signed value e8 to SP.
253 Cycles: 4
255 Bytes: 2
257 Flags:
259 · Z: 0
260 · N: 0
261 · H: Set if overflow from bit 3.
262 · C: Set if overflow from bit 7.
263 AND A,r8
265 Bitwise AND between the value in r8 and A.
266 Cycles: 1
268 Bytes: 1
270 Flags:
272 · Z: Set if result is 0.
273 · N: 0
274 · H: 1
275 · C: 0
276 AND A,[HL]
278 Bitwise AND between the value pointed by HL and A.
279 Cycles: 2
281 Bytes: 1
283 Flags: See AND A,r8
285 AND A,n8
287 Bitwise AND between the value in n8 and A.
288 Cycles: 2
290 Bytes: 2
292 Flags: See AND A,r8
294 BIT u3,r8
296 Test bit u3 in register r8, set the zero flag if bit not set.
297 Cycles: 2
299 Bytes: 2
301 Flags:
303 · Z: Set if the selected bit is 0.
304 · N: 0
305 · H: 1
306 BIT u3,[HL]
308 Test bit u3 in the byte pointed by HL, set the zero flag if bit not set.
309 Cycles: 3
311 Bytes: 2
313 Flags: See BIT u3,r8
315 CALL n16
317 Call address n16.
318 Cycles: 6
320 Bytes: 3
322 Flags: None affected.
324 CALL cc,n16
326 Call address n16 if condition cc is met.
327 Cycles: 6/3
329 Bytes: 3
331 Flags: None affected.
333 CCF
335 Complement Carry Flag.
336 Cycles: 1
338 Bytes: 1
340 Flags:
342 · N: 0
343 · H: 0
344 · C: Complemented.
345 CP A,r8
347 Subtract the value in r8 from A and set flags accordingly, but don't
348 store the result.
349 Cycles: 1
351 Bytes: 1
353 Flags:
355 · Z: Set if result is 0.
356 · N: 1
357 · H: Set if no borrow from bit 4.
358 · C: Set if no borrow (set if r8 > A).
359 CP A,[HL]
361 Subtract the value pointed by HL from A and set flags accordingly, but
362 don't store the result.
363 Cycles: 2
365 Bytes: 1
367 Flags: See CP A,r8
369 CP A,n8
371 Subtract the value n8 from A and set flags accordingly, but don't store
372 the result.
373 Cycles: 2
375 Bytes: 2
377 Flags: See CP A,r8
379 CPL
381 Complement accumulator (A = ~A).
382 Cycles: 1
384 Bytes: 1
386 Flags:
388 · N: 1
389 · H: 1
390 DAA
392 Decimal adjust register A to get a correct BCD representation after an
393 arithmetic instruction.
394 Cycles: 1
396 Bytes: 1
398 Flags:
400 · Z: Set if result is 0.
401 · H: 0
402 · C: Set or reset depending on the operation.
403 DEC r8
405 Decrement value in register r8 by 1.
406 Cycles: 1
408 Bytes: 1
410 Flags:
412 · Z: Set if result is 0.
413 · N: 1
414 · H: Set if no borrow from bit 4.
415 DEC [HL]
417 Decrement the value pointed by HL by 1.
418 Cycles: 3
420 Bytes: 1
422 Flags: See DEC r8
424 DEC r16
426 Decrement value in register r16 by 1.
427 Cycles: 2
429 Bytes: 1
431 Flags: None affected.
433 DEC SP
435 Decrement value in register SP by 1.
436 Cycles: 2
438 Bytes: 1
440 Flags: None affected.
442 DI
444 Disable Interrupts.
445 Cycles: 1
447 Bytes: 1
449 Flags: None affected.
451 EI
453 Enable Interrupts.
454 Cycles: 1
456 Bytes: 1
458 Flags: None affected.
460 HALT
462 Enter CPU low power mode.
463 Cycles: -
465 Bytes: 1
467 Flags: None affected.
469 INC r8
471 Increment value in register r8 by 1.
472 Cycles: 1
474 Bytes: 1
476 Flags:
478 · Z: Set if result is 0.
479 · N: 0
480 · H: Set if overflow from bit 3.
481 INC [HL]
483 Increment the value pointed by HL by 1.
484 Cycles: 3
486 Bytes: 1
488 Flags: See INC r8
490 INC r16
492 Increment value in register r16 by 1.
493 Cycles: 2
495 Bytes: 1
497 Flags: None affected.
499 INC SP
501 Increment value in register SP by 1.
502 Cycles: 2
504 Bytes: 1
506 Flags: None affected.
508 JP n16
510 Absolute jump to address n16.
511 Cycles: 4
513 Bytes: 3
515 Flags: None affected.
517 JP cc,n16
519 Absolute jump to address n16 if condition cc is met.
520 Cycles: 4/3
522 Bytes: 3
524 Flags: None affected.
526 JP HL
528 Jump to address in HL, that is, load PC with value in register HL.
529 Cycles: 1
531 Bytes: 1
533 Flags: None affected.
535 JR e8
537 Relative jump by adding e8 to the current address.
538 Cycles: 3
540 Bytes: 2
542 Flags: None affected.
544 JR cc,e8
546 Relative jump by adding e8 to the current address if condition cc is met.
547 Cycles: 3/2
549 Bytes: 2
551 Flags: None affected.
553 LD r8,r8
555 Store value in register on the right into register on the left.
556 Cycles: 1
558 Bytes: 1
560 Flags: None affected.
562 LD r8,n8
564 Load value n8 into register r8.
565 Cycles: 2
567 Bytes: 2
569 Flags: None affected.
571 LD r16,n16
573 Load value n16 into register r16.
574 Cycles: 3
576 Bytes: 3
578 Flags: None affected.
580 LD [HL],r8
582 Store value in register r8 into byte pointed by register HL.
583 Cycles: 2
585 Bytes: 1
587 Flags: None affected.
589 LD [HL],n8
591 Store value n8 into byte pointed by register HL.
592 Cycles: 3
594 Bytes: 2
596 Flags: None affected.
598 LD r8,[HL]
600 Load value into register r8 from byte pointed by register HL.
601 Cycles: 2
603 Bytes: 1
605 Flags: None affected.
607 LD [r16],A
609 Store value in register A into address pointed by register r16.
610 Cycles: 2
612 Bytes: 1
614 Flags: None affected.
616 LD [n16],A
618 Store value in register A into address n16.
619 Cycles: 4
621 Bytes: 3
623 Flags: None affected.
625 LD [$FF00+n8],A
627 Store value in register A into high RAM or I/O registers.
628 The following synonym forces this encoding: LDH [$FF00+n8],A
630 Cycles: 3
632 Bytes: 2
634 Flags: None affected.
636 LD [$FF00+C],A
638 Store value in register A into high RAM or I/O registers.
639 Cycles: 2
641 Bytes: 1
643 Flags: None affected.
645 LD A,[r16]
647 Load value in register A from address pointed by register r16.
648 Cycles: 2
650 Bytes: 1
652 Flags: None affected.
654 LD A,[n16]
656 Load value in register A from address n16.
657 Cycles: 4
659 Bytes: 3
661 Flags: None affected.
663 LD A,[$FF00+n8]
665 Load value in register A from high RAM or I/O registers.
666 The following synonym forces this encoding: LDH A,[$FF00+n8]
668 Cycles: 3
670 Bytes: 2
672 Flags: None affected.
674 LD A,[$FF00+C]
676 Load value in register A from high RAM or I/O registers.
677 Cycles: 2
679 Bytes: 1
681 Flags: None affected.
683 LD [HL+],A
685 Store value in register A into byte pointed by HL and post-increment HL.
686 Cycles: 2
688 Bytes: 1
690 Flags: None affected.
692 LD [HL-],A
694 Store value in register A into byte pointed by HL and post-decrement HL.
695 Cycles: 2
697 Bytes: 1
699 Flags: None affected.
701 LD A,[HL+]
703 Load value into register A from byte pointed by HL and post-increment HL.
704 Cycles: 2
706 Bytes: 1
708 Flags: None affected.
710 LD A,[HL-]
712 Load value into register A from byte pointed by HL and post-decrement HL.
713 Cycles: 2
715 Bytes: 1
717 Flags: None affected.
719 LD SP,n16
721 Load value n16 into register SP.
722 Cycles: 3
724 Bytes: 3
726 Flags: None affected.
728 LD [n16],SP
730 Store SP into addresses n16 (LSB) and n16 + 1 (MSB).
731 Cycles: 5
733 Bytes: 3
735 Flags: None affected.
737 LD HL,SP+e8
739 Add the signed value e8 to SP and store the result in HL.
740 Cycles: 3
742 Bytes: 2
744 Flags:
746 · Z: 0
747 · N: 0
748 · H: Set if overflow from bit 3.
749 · C: Set if overflow from bit 7.
750 LD SP,HL
752 Load register HL into register SP.
753 Cycles: 2
755 Bytes: 1
757 Flags: None affected.
759 NOP
761 No operation.
762 Cycles: 1
764 Bytes: 1
766 Flags: None affected.
768 OR A,r8
770 Bitwise OR between the value in r8 and A.
771 Cycles: 1
773 Bytes: 1
775 Flags:
777 · Z: Set if result is 0.
778 · N: 0
779 · H: 0
780 · C: 0
781 OR A,[HL]
783 Bitwise OR between the value pointed by HL and A.
784 Cycles: 2
786 Bytes: 1
788 Flags: See OR A,r8
790 OR A,n8
792 Bitwise OR between the value in n8 and A.
793 Cycles: 2
795 Bytes: 2
797 Flags: See OR A,r8
799 POP AF
801 Pop register AF from the stack.
802 Cycles: 3
804 Bytes: 1
806 Flags: None affected.
808 POP r16
810 Pop register r16 from the stack.
811 Cycles: 3
813 Bytes: 1
815 Flags: None affected.
817 PUSH AF
819 Push register AF into the stack.
820 Cycles: 4
822 Bytes: 1
824 Flags: None affected.
826 PUSH r16
828 Push register r16 into the stack.
829 Cycles: 4
831 Bytes: 1
833 Flags: None affected.
835 RES u3,r8
837 Set bit u3 in register r8 to 0.
838 Cycles: 2
840 Bytes: 2
842 Flags: None affected.
844 RES u3,[HL]
846 Set bit u3 in the byte pointed by HL to 0.
847 Cycles: 4
849 Bytes: 2
851 Flags: None affected.
853 RET
855 Return from subroutine.
856 Cycles: 4
858 Bytes: 1
860 Flags: None affected.
862 RET cc
864 Return from subroutine if condition cc is met.
865 Cycles: 5/2
867 Bytes: 1
869 Flags: None affected.
871 RETI
873 Return from subroutine and enable interrupts.
874 Cycles: 4
876 Bytes: 1
878 Flags: None affected.
880 RL r8
882 Rotate register r8 left through carry.
883 C <- [7 <- 0] <- C
885 Cycles: 2
887 Bytes: 2
889 Flags:
891 · Z: Set if result is 0.
892 · N: 0
893 · H: 0
894 · C: Set according to result.
895 RL [HL]
897 Rotate value pointed by HL left through carry.
898 C <- [7 <- 0] <- C
900 Cycles: 4
902 Bytes: 2
904 Flags: See RL r8
906 RLA
908 Rotate register A left through carry.
909 C <- [7 <- 0] <- C
911 Cycles: 1
913 Bytes: 1
915 Flags:
917 · Z: 0
918 · N: 0
919 · H: 0
920 · C: Set according to result.
921 RLC r8
923 Rotate register r8 left.
924 C <- [7 <- 0] <- [7]
926 Cycles: 2
928 Bytes: 2
930 Flags:
932 · Z: Set if result is 0.
933 · N: 0
934 · H: 0
935 · C: Set according to result.
936 RLC [HL]
938 Rotate value pointed by HL left.
939 C <- [7 <- 0] <- [7]
941 Cycles: 4
943 Bytes: 2
945 Flags: See RLC r8
947 RLCA
949 Rotate register A left.
950 C <- [7 <- 0] <- [7]
952 Cycles: 1
954 Bytes: 1
956 Flags:
958 · Z: 0
959 · N: 0
960 · H: 0
961 · C: Set according to result.
962 RR r8
964 Rotate register r8 right through carry.
965 C -> [7 -> 0] -> C
967 Cycles: 2
969 Bytes: 2
971 Flags:
973 · Z: Set if result is 0.
974 · N: 0
975 · H: 0
976 · C: Set according to result.
977 RR [HL]
979 Rotate value pointed by HL right through carry.
980 C -> [7 -> 0] -> C
982 Cycles: 4
984 Bytes: 2
986 Flags: See RR r8
988 RRA
990 Rotate register A right through carry.
991 C -> [7 -> 0] -> C
993 Cycles: 1
995 Bytes: 1
997 Flags:
999 · Z: 0
1000 · N: 0
1001 · H: 0
1002 · C: Set according to result.
1003 RRC r8
1005 Rotate register r8 right.
1006 [0] -> [7 -> 0] -> C
1008 Cycles: 2
1010 Bytes: 2
1012 Flags:
1014 · Z: Set if result is 0.
1015 · N: 0
1016 · H: 0
1017 · C: Set according to result.
1018 RRC [HL]
1020 Rotate value pointed by HL right.
1021 [0] -> [7 -> 0] -> C
1023 Cycles: 4
1025 Bytes: 2
1027 Flags: See RRC r8
1029 RRCA
1031 Rotate register A right.
1032 [0] -> [7 -> 0] -> C
1034 Cycles: 1
1036 Bytes: 1
1038 Flags:
1040 · Z: 0
1041 · N: 0
1042 · H: 0
1043 · C: Set according to result.
1044 RST vec
1046 Call restart vector vec.
1047 Cycles: 4
1049 Bytes: 1
1051 Flags: None affected.
1053 SBC A,r8
1055 Subtract the value in r8 and the carry flag from A.
1056 Cycles: 1
1058 Bytes: 1
1060 Flags:
1062 · Z: Set if result is 0.
1063 · N: 1
1064 · H: Set if no borrow from bit 4.
1065 · C: Set if no borrow (set if r8 > A).
1066 SBC A,[HL]
1068 Subtract the value pointed by HL and the carry flag from A.
1069 Cycles: 2
1071 Bytes: 1
1073 Flags: See SBC A,r8
1075 SBC A,n8
1077 Subtract the value n8 and the carry flag from A.
1078 Cycles: 2
1080 Bytes: 2
1082 Flags: See SBC A,r8
1084 SCF
1086 Set Carry Flag.
1087 Cycles: 1
1089 Bytes: 1
1091 Flags:
1093 · N: 0
1094 · H: 0
1095 · C: 1
1096 SET u3,r8
1098 Set bit u3 in register r8 to 1.
1099 Cycles: 2
1101 Bytes: 2
1103 Flags: None affected.
1105 SET u3,[HL]
1107 Set bit u3 in the byte pointed by HL to 1.
1108 Cycles: 4
1110 Bytes: 2
1112 Flags: None affected.
1114 SLA r8
1116 Shift left arithmetic register r8.
1117 C <- [7 <- 0] <- 0
1119 Cycles: 2
1121 Bytes: 2
1123 Flags:
1125 · Z: Set if result is 0.
1126 · N: 0
1127 · H: 0
1128 · C: Set according to result.
1129 SLA [HL]
1131 Shift left arithmetic value pointed by HL.
1132 C <- [7 <- 0] <- 0
1134 Cycles: 4
1136 Bytes: 2
1138 Flags: See SLA r8
1140 SRA r8
1142 Shift right arithmetic register r8.
1143 [7] -> [7 -> 0] -> C
1145 Cycles: 2
1147 Bytes: 2
1149 Flags:
1151 · Z: Set if result is 0.
1152 · N: 0
1153 · H: 0
1154 · C: Set according to result.
1155 SRA [HL]
1157 Shift right arithmetic value pointed by HL.
1158 [7] -> [7 -> 0] -> C
1160 Cycles: 4
1162 Bytes: 2
1164 Flags: See SRA r8
1166 SRL r8
1168 Shift right logic register r8.
1169 0 -> [7 -> 0] -> C
1171 Cycles: 2
1173 Bytes: 2
1175 Flags:
1177 · Z: Set if result is 0.
1178 · N: 0
1179 · H: 0
1180 · C: Set according to result.
1181 SRL [HL]
1183 Shift right logic value pointed by HL.
1184 0 -> [7 -> 0] -> C
1186 Cycles: 4
1188 Bytes: 2
1190 Flags: See SRA r8
1192 STOP
1194 Enter CPU very low power mode. Also used to switch between doube speed
1195 and normal CPU modes in GBC.
1196 Cycles: -
1198 Bytes: 2
1200 Flags: None affected.
1202 SUB A,r8
1204 Subtract the value in r8 from A.
1205 Cycles: 1
1207 Bytes: 1
1209 Flags:
1211 · Z: Set if result is 0.
1212 · N: 1
1213 · H: Set if no borrow from bit 4.
1214 · C: Set if no borrow (set if r8 > A).
1215 SUB A,[HL]
1217 Subtract the value pointed by HL from A.
1218 Cycles: 2
1220 Bytes: 1
1222 Flags: See SUB A,r8
1224 SUB A,n8
1226 Subtract the value n8 from A.
1227 Cycles: 2
1229 Bytes: 2
1231 Flags: See SUB A,r8
1233 SWAP r8
1235 Swap upper 4 bits in register r8 and the lower ones.
1236 Cycles: 2
1238 Bytes: 2
1240 Flags:
1242 · Z: Set if result is 0.
1243 · N: 0
1244 · H: 0
1245 · C: 0
1246 SWAP [HL]
1248 Swap upper 4 bits in the byte pointed by HL and the lower ones.
1249 Cycles: 4
1251 Bytes: 2
1253 Flags: See SWAP r8
1255 XOR A,r8
1257 Bitwise XOR between the value in r8 and A.
1258 Cycles: 1
1260 Bytes: 1
1262 Flags:
1264 · Z: Set if result is 0.
1265 · N: 0
1266 · H: 0
1267 · C: 0
1268 XOR A,[HL]
1270 Bitwise XOR between the value pointed by HL and A.
1271 Cycles: 2
1273 Bytes: 1
1275 Flags: See XOR A,r8
1277 XOR A,n8
1279 Bitwise XOR between the value in n8 and A.
1280 Cycles: 2
1282 Bytes: 2
1284 Flags: See XOR A,r8
1286
1288 rgbasm(1), rgbds(7)
1289
1291 rgbds was originally written by Carsten Sørensen as part of the ASMotor
1292 package, and was later packaged in RGBDS by Justin Lloyd. It is now
1293 maintained by a number of contributors at .:
1294 https://github.com/rednex/rgbds
1295RGBDS Manual April 17, 2017 RGBDS Manual