1AS(1) GNU Development Tools AS(1)
2
3
4
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14 [--help] [-I dir] [-J]
15 [-K] [-L] [--listing-lhs-width=NUM]
16 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17 [--listing-cont-lines=NUM] [--keep-locals]
18 [--no-pad-sections]
19 [-o objfile] [-R]
20 [--hash-size=NUM] [--reduce-memory-overheads]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--target-help] [target-options]
28 [--|files ...]
29
31 Target AArch64 options:
32 [-EB|-EL]
33 [-mabi=ABI]
34
35 Target Alpha options:
36 [-mcpu]
37 [-mdebug | -no-mdebug]
38 [-replace | -noreplace]
39 [-relax] [-g] [-Gsize]
40 [-F] [-32addr]
41
42 Target ARC options:
43 [-mcpu=cpu]
44 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
45 [-mcode-density]
46 [-mrelax]
47 [-EB|-EL]
48
49 Target ARM options:
50 [-mcpu=processor[+extension...]]
51 [-march=architecture[+extension...]]
52 [-mfpu=floating-point-format]
53 [-mfloat-abi=abi]
54 [-meabi=ver]
55 [-mthumb]
56 [-EB|-EL]
57 [-mapcs-32|-mapcs-26|-mapcs-float|
58 -mapcs-reentrant]
59 [-mthumb-interwork] [-k]
60
61 Target Blackfin options:
62 [-mcpu=processor[-sirevision]]
63 [-mfdpic]
64 [-mno-fdpic]
65 [-mnopic]
66
67 Target CRIS options:
68 [--underscore | --no-underscore]
69 [--pic] [-N]
70 [--emulation=criself | --emulation=crisaout]
71 [--march=v0_v10 | --march=v10 | --march=v32 |
72 --march=common_v10_v32]
73
74 Target D10V options:
75 [-O]
76
77 Target D30V options:
78 [-O|-n|-N]
79
80 Target EPIPHANY options:
81 [-mepiphany|-mepiphany16]
82
83 Target H8/300 options:
84 [-h-tick-hex]
85
86 Target i386 options:
87 [--32|--x32|--64] [-n]
88 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
89
90 Target i960 options:
91 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
92 -AKC|-AMC]
93 [-b] [-no-relax]
94
95 Target IA-64 options:
96 [-mconstant-gp|-mauto-pic]
97 [-milp32|-milp64|-mlp64|-mp64]
98 [-mle|mbe]
99 [-mtune=itanium1|-mtune=itanium2]
100 [-munwind-check=warning|-munwind-check=error]
101 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
102 [-x|-xexplicit] [-xauto] [-xdebug]
103
104 Target IP2K options:
105 [-mip2022|-mip2022ext]
106
107 Target M32C options:
108 [-m32c|-m16c] [-relax] [-h-tick-hex]
109
110 Target M32R options:
111 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
112 --W[n]p]
113
114 Target M680X0 options:
115 [-l] [-m68000|-m68010|-m68020|...]
116
117 Target M68HC11 options:
118 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
119 [-mshort|-mlong]
120 [-mshort-double|-mlong-double]
121 [--force-long-branches] [--short-branches]
122 [--strict-direct-mode] [--print-insn-syntax]
123 [--print-opcodes] [--generate-example]
124
125 Target MCORE options:
126 [-jsri2bsr] [-sifilter] [-relax]
127 [-mcpu=[210|340]]
128
129 Target Meta options:
130 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
131
132 Target MIPS options:
133 [-nocpp] [-EL] [-EB] [-O[optimization level]]
134 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
135 [-non_shared] [-xgot [-mvxworks-pic]
136 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
137 [-mfp64] [-mgp64] [-mfpxx]
138 [-modd-spreg] [-mno-odd-spreg]
139 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
140 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
141 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
142 [-mips64r3] [-mips64r5] [-mips64r6]
143 [-construct-floats] [-no-construct-floats]
144 [-mnan=encoding]
145 [-trap] [-no-break] [-break] [-no-trap]
146 [-mips16] [-no-mips16]
147 [-mmicromips] [-mno-micromips]
148 [-msmartmips] [-mno-smartmips]
149 [-mips3d] [-no-mips3d]
150 [-mdmx] [-no-mdmx]
151 [-mdsp] [-mno-dsp]
152 [-mdspr2] [-mno-dspr2]
153 [-mdspr3] [-mno-dspr3]
154 [-mmsa] [-mno-msa]
155 [-mxpa] [-mno-xpa]
156 [-mmt] [-mno-mt]
157 [-mmcu] [-mno-mcu]
158 [-minsn32] [-mno-insn32]
159 [-mfix7000] [-mno-fix7000]
160 [-mfix-rm7000] [-mno-fix-rm7000]
161 [-mfix-vr4120] [-mno-fix-vr4120]
162 [-mfix-vr4130] [-mno-fix-vr4130]
163 [-mdebug] [-no-mdebug]
164 [-mpdr] [-mno-pdr]
165
166 Target MMIX options:
167 [--fixed-special-register-names] [--globalize-symbols]
168 [--gnu-syntax] [--relax] [--no-predefined-symbols]
169 [--no-expand] [--no-merge-gregs] [-x]
170 [--linker-allocated-gregs]
171
172 Target Nios II options:
173 [-relax-all] [-relax-section] [-no-relax]
174 [-EB] [-EL]
175
176 Target NDS32 options:
177 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
178 [-misa=isa] [-mabi=abi] [-mall-ext]
179 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
180 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
181 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
182 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
183 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
184 [-mb2bb]
185
186 Target PDP11 options:
187 [-mpic|-mno-pic] [-mall] [-mno-extensions]
188 [-mextension|-mno-extension]
189 [-mcpu] [-mmachine]
190
191 Target picoJava options:
192 [-mb|-me]
193
194 Target PowerPC options:
195 [-a32|-a64]
196 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
197 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
198 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
199 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
200 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
201 -mcell|-mspe|-mtitan|-me300|-mcom]
202 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
203 [-mregnames|-mno-regnames]
204 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
205 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
206 [-msolaris|-mno-solaris]
207 [-nops=count]
208
209 Target RL78 options:
210 [-mg10]
211 [-m32bit-doubles|-m64bit-doubles]
212
213 Target RX options:
214 [-mlittle-endian|-mbig-endian]
215 [-m32bit-doubles|-m64bit-doubles]
216 [-muse-conventional-section-names]
217 [-msmall-data-limit]
218 [-mpid]
219 [-mrelax]
220 [-mint-register=number]
221 [-mgcc-abi|-mrx-abi]
222
223 Target s390 options:
224 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
225 [-mregnames|-mno-regnames]
226 [-mwarn-areg-zero]
227
228 Target SCORE options:
229 [-EB][-EL][-FIXDD][-NWARN]
230 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
231 [-march=score7][-march=score3]
232 [-USE_R1][-KPIC][-O0][-G num][-V]
233
234 Target SPARC options:
235 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
236 -Av8plus|-Av8plusa|-Av9|-Av9a]
237 [-xarch=v8plus|-xarch=v8plusa] [-bump]
238 [-32|-64]
239
240 Target TIC54X options:
241 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
242 [-merrors-to-file <filename>|-me <filename>]
243
244 Target TIC6X options:
245 [-march=arch] [-mbig-endian|-mlittle-endian]
246 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
247 [-mpic|-mno-pic]
248
249 Target TILE-Gx options:
250 [-m32|-m64][-EB][-EL]
251
252 Target Visium options:
253 [-mtune=arch]
254
255 Target Xtensa options:
256 [--[no-]text-section-literals] [--[no-]auto-litpools]
257 [--[no-]absolute-literals]
258 [--[no-]target-align] [--[no-]longcalls]
259 [--[no-]transform]
260 [--rename-section oldname=newname]
261 [--[no-]trampolines]
262
263 Target Z80 options:
264 [-z80] [-r800]
265 [ -ignore-undocumented-instructions] [-Wnud]
266 [ -ignore-unportable-instructions] [-Wnup]
267 [ -warn-undocumented-instructions] [-Wud]
268 [ -warn-unportable-instructions] [-Wup]
269 [ -forbid-undocumented-instructions] [-Fud]
270 [ -forbid-unportable-instructions] [-Fup]
271
273 GNU as is really a family of assemblers. If you use (or have used) the
274 GNU assembler on one architecture, you should find a fairly similar
275 environment when you use it on another architecture. Each version has
276 much in common with the others, including object file formats, most
277 assembler directives (often called pseudo-ops) and assembler syntax.
278
279 as is primarily intended to assemble the output of the GNU C compiler
280 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
281 assemble correctly everything that other assemblers for the same
282 machine would assemble. Any exceptions are documented explicitly.
283 This doesn't mean as always uses the same syntax as another assembler
284 for the same architecture; for example, we know of several incompatible
285 versions of 680x0 assembly language syntax.
286
287 Each time you run as it assembles exactly one source program. The
288 source program is made up of one or more files. (The standard input is
289 also a file.)
290
291 You give as a command line that has zero or more input file names. The
292 input files are read (from left file name to right). A command line
293 argument (in any position) that has no special meaning is taken to be
294 an input file name.
295
296 If you give as no file names it attempts to read one input file from
297 the as standard input, which is normally your terminal. You may have
298 to type ctl-D to tell as there is no more program to assemble.
299
300 Use -- if you need to explicitly name the standard input file in your
301 command line.
302
303 If the source is empty, as produces a small, empty object file.
304
305 as may write warnings and error messages to the standard error file
306 (usually your terminal). This should not happen when a compiler runs
307 as automatically. Warnings report an assumption made so that as could
308 keep assembling a flawed program; errors report a grave problem that
309 stops the assembly.
310
311 If you are invoking as via the GNU C compiler, you can use the -Wa
312 option to pass arguments through to the assembler. The assembler
313 arguments must be separated from each other (and the -Wa) by commas.
314 For example:
315
316 gcc -c -g -O -Wa,-alh,-L file.c
317
318 This passes two options to the assembler: -alh (emit a listing to
319 standard output with high-level and assembly source) and -L (retain
320 local symbols in the symbol table).
321
322 Usually you do not need to use this -Wa mechanism, since many compiler
323 command-line options are automatically passed to the assembler by the
324 compiler. (You can call the GNU compiler driver with the -v option to
325 see precisely what options it passes to each compilation pass,
326 including the assembler.)
327
329 @file
330 Read command-line options from file. The options read are inserted
331 in place of the original @file option. If file does not exist, or
332 cannot be read, then the option will be treated literally, and not
333 removed.
334
335 Options in file are separated by whitespace. A whitespace
336 character may be included in an option by surrounding the entire
337 option in either single or double quotes. Any character (including
338 a backslash) may be included by prefixing the character to be
339 included with a backslash. The file may itself contain additional
340 @file options; any such options will be processed recursively.
341
342 -a[cdghlmns]
343 Turn on listings, in any of a variety of ways:
344
345 -ac omit false conditionals
346
347 -ad omit debugging directives
348
349 -ag include general information, like as version and options passed
350
351 -ah include high-level source
352
353 -al include assembly
354
355 -am include macro expansions
356
357 -an omit forms processing
358
359 -as include symbols
360
361 =file
362 set the name of the listing file
363
364 You may combine these options; for example, use -aln for assembly
365 listing without forms processing. The =file option, if used, must
366 be the last one. By itself, -a defaults to -ahls.
367
368 --alternate
369 Begin in alternate macro mode.
370
371 --compress-debug-sections
372 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
373 the ELF ABI. The resulting object file may not be compatible with
374 older linkers and object file utilities. Note if compression would
375 make a given section larger then it is not compressed.
376
377 --compress-debug-sections=none
378 --compress-debug-sections=zlib
379 --compress-debug-sections=zlib-gnu
380 --compress-debug-sections=zlib-gabi
381 These options control how DWARF debug sections are compressed.
382 --compress-debug-sections=none is equivalent to
383 --nocompress-debug-sections. --compress-debug-sections=zlib and
384 --compress-debug-sections=zlib-gabi are equivalent to
385 --compress-debug-sections. --compress-debug-sections=zlib-gnu
386 compresses DWARF debug sections using zlib. The debug sections are
387 renamed to begin with .zdebug. Note if compression would make a
388 given section larger then it is not compressed nor renamed.
389
390 --nocompress-debug-sections
391 Do not compress DWARF debug sections. This is usually the default
392 for all targets except the x86/x86_64, but a configure time option
393 can be used to override this.
394
395 -D Ignored. This option is accepted for script compatibility with
396 calls to other assemblers.
397
398 --debug-prefix-map old=new
399 When assembling files in directory old, record debugging
400 information describing them as in new instead.
401
402 --defsym sym=value
403 Define the symbol sym to be value before assembling the input file.
404 value must be an integer constant. As in C, a leading 0x indicates
405 a hexadecimal value, and a leading 0 indicates an octal value. The
406 value of the symbol can be overridden inside a source file via the
407 use of a ".set" pseudo-op.
408
409 -f "fast"---skip whitespace and comment preprocessing (assume source
410 is compiler output).
411
412 -g
413 --gen-debug
414 Generate debugging information for each assembler source line using
415 whichever debug format is preferred by the target. This currently
416 means either STABS, ECOFF or DWARF2.
417
418 --gstabs
419 Generate stabs debugging information for each assembler line. This
420 may help debugging assembler code, if the debugger can handle it.
421
422 --gstabs+
423 Generate stabs debugging information for each assembler line, with
424 GNU extensions that probably only gdb can handle, and that could
425 make other debuggers crash or refuse to read your program. This
426 may help debugging assembler code. Currently the only GNU
427 extension is the location of the current working directory at
428 assembling time.
429
430 --gdwarf-2
431 Generate DWARF2 debugging information for each assembler line.
432 This may help debugging assembler code, if the debugger can handle
433 it. Note---this option is only supported by some targets, not all
434 of them.
435
436 --gdwarf-sections
437 Instead of creating a .debug_line section, create a series of
438 .debug_line.foo sections where foo is the name of the corresponding
439 code section. For example a code section called .text.func will
440 have its dwarf line number information placed into a section called
441 .debug_line.text.func. If the code section is just called .text
442 then debug line section will still be called just .debug_line
443 without any suffix.
444
445 --size-check=error
446 --size-check=warning
447 Issue an error or warning for invalid ELF .size directive.
448
449 --elf-stt-common=no
450 --elf-stt-common=yes
451 These options control whether the ELF assembler should generate
452 common symbols with the "STT_COMMON" type. The default can be
453 controlled by a configure option --enable-elf-stt-common.
454
455 --help
456 Print a summary of the command line options and exit.
457
458 --target-help
459 Print a summary of all target specific options and exit.
460
461 -I dir
462 Add directory dir to the search list for ".include" directives.
463
464 -J Don't warn about signed overflow.
465
466 -K Issue warnings when difference tables altered for long
467 displacements.
468
469 -L
470 --keep-locals
471 Keep (in the symbol table) local symbols. These symbols start with
472 system-specific local label prefixes, typically .L for ELF systems
473 or L for traditional a.out systems.
474
475 --listing-lhs-width=number
476 Set the maximum width, in words, of the output data column for an
477 assembler listing to number.
478
479 --listing-lhs-width2=number
480 Set the maximum width, in words, of the output data column for
481 continuation lines in an assembler listing to number.
482
483 --listing-rhs-width=number
484 Set the maximum width of an input source line, as displayed in a
485 listing, to number bytes.
486
487 --listing-cont-lines=number
488 Set the maximum number of lines printed in a listing for a single
489 line of input to number + 1.
490
491 --no-pad-sections
492 Stop the assembler for padding the ends of output sections to the
493 alignment of that section. The default is to pad the sections, but
494 this can waste space which might be needed on targets which have
495 tight memory constraints.
496
497 -o objfile
498 Name the object-file output from as objfile.
499
500 -R Fold the data section into the text section.
501
502 --hash-size=number
503 Set the default size of GAS's hash tables to a prime number close
504 to number. Increasing this value can reduce the length of time it
505 takes the assembler to perform its tasks, at the expense of
506 increasing the assembler's memory requirements. Similarly reducing
507 this value can reduce the memory requirements at the expense of
508 speed.
509
510 --reduce-memory-overheads
511 This option reduces GAS's memory requirements, at the expense of
512 making the assembly processes slower. Currently this switch is a
513 synonym for --hash-size=4051, but in the future it may have other
514 effects as well.
515
516 --sectname-subst
517 Honor substitution sequences in section names.
518
519 --statistics
520 Print the maximum space (in bytes) and total time (in seconds) used
521 by assembly.
522
523 --strip-local-absolute
524 Remove local absolute symbols from the outgoing symbol table.
525
526 -v
527 -version
528 Print the as version.
529
530 --version
531 Print the as version and exit.
532
533 -W
534 --no-warn
535 Suppress warning messages.
536
537 --fatal-warnings
538 Treat warnings as errors.
539
540 --warn
541 Don't suppress warning messages or treat them as errors.
542
543 -w Ignored.
544
545 -x Ignored.
546
547 -Z Generate an object file even after errors.
548
549 -- | files ...
550 Standard input, or source files to assemble.
551
552 The following options are available when as is configured for the
553 64-bit mode of the ARM Architecture (AArch64).
554
555 -EB This option specifies that the output generated by the assembler
556 should be marked as being encoded for a big-endian processor.
557
558 -EL This option specifies that the output generated by the assembler
559 should be marked as being encoded for a little-endian processor.
560
561 -mabi=abi
562 Specify which ABI the source code uses. The recognized arguments
563 are: "ilp32" and "lp64", which decides the generated object file in
564 ELF32 and ELF64 format respectively. The default is "lp64".
565
566 -mcpu=processor[+extension...]
567 This option specifies the target processor. The assembler will
568 issue an error message if an attempt is made to assemble an
569 instruction which will not execute on the target processor. The
570 following processor names are recognized: "cortex-a35",
571 "cortex-a53", "cortex-a57", "cortex-a72", "cortex-a73",
572 "exynos-m1", "qdf24xx", "thunderx", "vulcan", "xgene1" and
573 "xgene2". The special name "all" may be used to allow the
574 assembler to accept instructions valid for any supported processor,
575 including all optional extensions.
576
577 In addition to the basic instruction set, the assembler can be told
578 to accept, or restrict, various extension mnemonics that extend the
579 processor.
580
581 If some implementations of a particular processor can have an
582 extension, then then those extensions are automatically enabled.
583 Consequently, you will not normally have to specify any additional
584 extensions.
585
586 -march=architecture[+extension...]
587 This option specifies the target architecture. The assembler will
588 issue an error message if an attempt is made to assemble an
589 instruction which will not execute on the target architecture. The
590 following architecture names are recognized: "armv8-a", "armv8.1-a"
591 and "armv8.2-a".
592
593 If both -mcpu and -march are specified, the assembler will use the
594 setting for -mcpu. If neither are specified, the assembler will
595 default to -mcpu=all.
596
597 The architecture option can be extended with the same instruction
598 set extension options as the -mcpu option. Unlike -mcpu,
599 extensions are not always enabled by default,
600
601 -mverbose-error
602 This option enables verbose error messages for AArch64 gas. This
603 option is enabled by default.
604
605 -mno-verbose-error
606 This option disables verbose error messages in AArch64 gas.
607
608 The following options are available when as is configured for an Alpha
609 processor.
610
611 -mcpu
612 This option specifies the target processor. If an attempt is made
613 to assemble an instruction which will not execute on the target
614 processor, the assembler may either expand the instruction as a
615 macro or issue an error message. This option is equivalent to the
616 ".arch" directive.
617
618 The following processor names are recognized: 21064, "21064a",
619 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
620 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
621 "ev67", "ev68". The special name "all" may be used to allow the
622 assembler to accept instructions valid for any Alpha processor.
623
624 In order to support existing practice in OSF/1 with respect to
625 ".arch", and existing practice within MILO (the Linux ARC
626 bootloader), the numbered processor names (e.g. 21064) enable the
627 processor-specific PALcode instructions, while the "electro-vlasic"
628 names (e.g. "ev4") do not.
629
630 -mdebug
631 -no-mdebug
632 Enables or disables the generation of ".mdebug" encapsulation for
633 stabs directives and procedure descriptors. The default is to
634 automatically enable ".mdebug" when the first stabs directive is
635 seen.
636
637 -relax
638 This option forces all relocations to be put into the object file,
639 instead of saving space and resolving some relocations at assembly
640 time. Note that this option does not propagate all symbol
641 arithmetic into the object file, because not all symbol arithmetic
642 can be represented. However, the option can still be useful in
643 specific applications.
644
645 -replace
646 -noreplace
647 Enables or disables the optimization of procedure calls, both at
648 assemblage and at link time. These options are only available for
649 VMS targets and "-replace" is the default. See section 1.4.1 of
650 the OpenVMS Linker Utility Manual.
651
652 -g This option is used when the compiler generates debug information.
653 When gcc is using mips-tfile to generate debug information for
654 ECOFF, local labels must be passed through to the object file.
655 Otherwise this option has no effect.
656
657 -Gsize
658 A local common symbol larger than size is placed in ".bss", while
659 smaller symbols are placed in ".sbss".
660
661 -F
662 -32addr
663 These options are ignored for backward compatibility.
664
665 The following options are available when as is configured for an ARC
666 processor.
667
668 -mcpu=cpu
669 This option selects the core processor variant.
670
671 -EB | -EL
672 Select either big-endian (-EB) or little-endian (-EL) output.
673
674 -mcode-density
675 Enable Code Density extenssion instructions.
676
677 The following options are available when as is configured for the ARM
678 processor family.
679
680 -mcpu=processor[+extension...]
681 Specify which ARM processor variant is the target.
682
683 -march=architecture[+extension...]
684 Specify which ARM architecture variant is used by the target.
685
686 -mfpu=floating-point-format
687 Select which Floating Point architecture is the target.
688
689 -mfloat-abi=abi
690 Select which floating point ABI is in use.
691
692 -mthumb
693 Enable Thumb only instruction decoding.
694
695 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
696 Select which procedure calling convention is in use.
697
698 -EB | -EL
699 Select either big-endian (-EB) or little-endian (-EL) output.
700
701 -mthumb-interwork
702 Specify that the code has been generated with interworking between
703 Thumb and ARM code in mind.
704
705 -mccs
706 Turns on CodeComposer Studio assembly syntax compatibility mode.
707
708 -k Specify that PIC code has been generated.
709
710 The following options are available when as is configured for the
711 Blackfin processor family.
712
713 -mcpu=processor[-sirevision]
714 This option specifies the target processor. The optional
715 sirevision is not used in assembler. It's here such that GCC can
716 easily pass down its "-mcpu=" option. The assembler will issue an
717 error message if an attempt is made to assemble an instruction
718 which will not execute on the target processor. The following
719 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
720 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
721 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
722 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
723 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
724 "bf549", "bf549m", "bf561", and "bf592".
725
726 -mfdpic
727 Assemble for the FDPIC ABI.
728
729 -mno-fdpic
730 -mnopic
731 Disable -mfdpic.
732
733 See the info pages for documentation of the CRIS-specific options.
734
735 The following options are available when as is configured for a D10V
736 processor.
737
738 -O Optimize output by parallelizing instructions.
739
740 The following options are available when as is configured for a D30V
741 processor.
742
743 -O Optimize output by parallelizing instructions.
744
745 -n Warn when nops are generated.
746
747 -N Warn when a nop after a 32-bit multiply instruction is generated.
748
749 The following options are available when as is configured for an
750 Epiphany processor.
751
752 -mepiphany
753 Specifies that the both 32 and 16 bit instructions are allowed.
754 This is the default behavior.
755
756 -mepiphany16
757 Restricts the permitted instructions to just the 16 bit set.
758
759 The following options are available when as is configured for an H8/300
760 processor. @chapter H8/300 Dependent Features
761
762 Options
763 The Renesas H8/300 version of "as" has one machine-dependent option:
764
765 -h-tick-hex
766 Support H'00 style hex constants in addition to 0x00 style.
767
768 -mach=name
769 Sets the H8300 machine variant. The following machine names are
770 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
771 "h8300sxn".
772
773 The following options are available when as is configured for an i386
774 processor.
775
776 --32 | --x32 | --64
777 Select the word size, either 32 bits or 64 bits. --32 implies
778 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
779 architecture with 32-bit or 64-bit word-size respectively.
780
781 These options are only available with the ELF object file format,
782 and require that the necessary BFD support has been included (on a
783 32-bit platform you have to add --enable-64-bit-bfd to configure
784 enable 64-bit usage and use x86-64 as target platform).
785
786 -n By default, x86 GAS replaces multiple nop instructions used for
787 alignment within code sections with multi-byte nop instructions
788 such as leal 0(%esi,1),%esi. This switch disables the
789 optimization.
790
791 --divide
792 On SVR4-derived platforms, the character / is treated as a comment
793 character, which means that it cannot be used in expressions. The
794 --divide option turns / into a normal character. This does not
795 disable / at the beginning of a line starting a comment, or affect
796 using # for starting a comment.
797
798 -march=CPU[+EXTENSION...]
799 This option specifies the target processor. The assembler will
800 issue an error message if an attempt is made to assemble an
801 instruction which will not execute on the target processor. The
802 following processor names are recognized: "i8086", "i186", "i286",
803 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
804 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
805 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
806 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
807 "bdver3", "bdver4", "znver1", "btver1", "btver2", "generic32" and
808 "generic64".
809
810 In addition to the basic instruction set, the assembler can be told
811 to accept various extension mnemonics. For example,
812 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
813 following extensions are currently supported: 8087, 287, 387, 687,
814 "no87", "no287", "no387", "no687", "mmx", "nommx", "sse", "sse2",
815 "sse3", "ssse3", "sse4.1", "sse4.2", "sse4", "nosse", "nosse2",
816 "nosse3", "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx",
817 "avx2", "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap",
818 "mpx", "sha", "rdpid", "prefetchwt1", "clflushopt", "se1", "clwb",
819 "pcommit", "avx512f", "avx512cd", "avx512er", "avx512pf",
820 "avx512vl", "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
821 "noavx512f", "noavx512cd", "noavx512er", "noavx512pf",
822 "noavx512vl", "noavx512bw", "noavx512dq", "noavx512ifma",
823 "noavx512vbmi", "vmx", "vmfunc", "smx", "xsave", "xsaveopt",
824 "xsavec", "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c",
825 "bmi2", "fma", "movbe", "ept", "lzcnt", "hle", "rtm", "invpcid",
826 "clflush", "mwaitx", "clzero", "lwp", "fma4", "xop", "cx16",
827 "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme",
828 "abm" and "padlock". Note that rather than extending a basic
829 instruction set, the extension mnemonics starting with "no" revoke
830 the respective functionality.
831
832 When the ".arch" directive is used with -march, the ".arch"
833 directive will take precedent.
834
835 -mtune=CPU
836 This option specifies a processor to optimize for. When used in
837 conjunction with the -march option, only instructions of the
838 processor specified by the -march option will be generated.
839
840 Valid CPU values are identical to the processor list of -march=CPU.
841
842 -msse2avx
843 This option specifies that the assembler should encode SSE
844 instructions with VEX prefix.
845
846 -msse-check=none
847 -msse-check=warning
848 -msse-check=error
849 These options control if the assembler should check SSE
850 instructions. -msse-check=none will make the assembler not to
851 check SSE instructions, which is the default. -msse-check=warning
852 will make the assembler issue a warning for any SSE instruction.
853 -msse-check=error will make the assembler issue an error for any
854 SSE instruction.
855
856 -mavxscalar=128
857 -mavxscalar=256
858 These options control how the assembler should encode scalar AVX
859 instructions. -mavxscalar=128 will encode scalar AVX instructions
860 with 128bit vector length, which is the default. -mavxscalar=256
861 will encode scalar AVX instructions with 256bit vector length.
862
863 -mevexlig=128
864 -mevexlig=256
865 -mevexlig=512
866 These options control how the assembler should encode length-
867 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
868 EVEX instructions with 128bit vector length, which is the default.
869 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
870 with 256bit and 512bit vector length, respectively.
871
872 -mevexwig=0
873 -mevexwig=1
874 These options control how the assembler should encode w-ignored
875 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
876 instructions with evex.w = 0, which is the default. -mevexwig=1
877 will encode WIG EVEX instructions with evex.w = 1.
878
879 -mmnemonic=att
880 -mmnemonic=intel
881 This option specifies instruction mnemonic for matching
882 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
883 will take precedent.
884
885 -msyntax=att
886 -msyntax=intel
887 This option specifies instruction syntax when processing
888 instructions. The ".att_syntax" and ".intel_syntax" directives
889 will take precedent.
890
891 -mnaked-reg
892 This opetion specifies that registers don't require a % prefix.
893 The ".att_syntax" and ".intel_syntax" directives will take
894 precedent.
895
896 -madd-bnd-prefix
897 This option forces the assembler to add BND prefix to all branches,
898 even if such prefix was not explicitly specified in the source
899 code.
900
901 -mno-shared
902 On ELF target, the assembler normally optimizes out non-PLT
903 relocations against defined non-weak global branch targets with
904 default visibility. The -mshared option tells the assembler to
905 generate code which may go into a shared library where all non-weak
906 global branch targets with default visibility can be preempted.
907 The resulting code is slightly bigger. This option only affects
908 the handling of branch instructions.
909
910 -mbig-obj
911 On x86-64 PE/COFF target this option forces the use of big object
912 file format, which allows more than 32768 sections.
913
914 -momit-lock-prefix=no
915 -momit-lock-prefix=yes
916 These options control how the assembler should encode lock prefix.
917 This option is intended as a workaround for processors, that fail
918 on lock prefix. This option can only be safely used with single-
919 core, single-thread computers -momit-lock-prefix=yes will omit all
920 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
921 usual, which is the default.
922
923 -mfence-as-lock-add=no
924 -mfence-as-lock-add=yes
925 These options control how the assembler should encode lfence,
926 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
927 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
928 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
929 encode lfence, mfence and sfence as usual, which is the default.
930
931 -mrelax-relocations=no
932 -mrelax-relocations=yes
933 These options control whether the assembler should generate relax
934 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
935 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
936 -mrelax-relocations=yes will generate relax relocations.
937 -mrelax-relocations=no will not generate relax relocations. The
938 default can be controlled by a configure option
939 --enable-x86-relax-relocations.
940
941 -mevexrcig=rne
942 -mevexrcig=rd
943 -mevexrcig=ru
944 -mevexrcig=rz
945 These options control how the assembler should encode SAE-only EVEX
946 instructions. -mevexrcig=rne will encode RC bits of EVEX
947 instruction with 00, which is the default. -mevexrcig=rd,
948 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
949 instructions with 01, 10 and 11 RC bits, respectively.
950
951 -mamd64
952 -mintel64
953 This option specifies that the assembler should accept only AMD64
954 or Intel64 ISA in 64-bit mode. The default is to accept both.
955
956 The following options are available when as is configured for the Intel
957 80960 processor.
958
959 -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
960 Specify which variant of the 960 architecture is the target.
961
962 -b Add code to collect statistics about branches taken.
963
964 -no-relax
965 Do not alter compare-and-branch instructions for long
966 displacements; error if necessary.
967
968 The following options are available when as is configured for the
969 Ubicom IP2K series.
970
971 -mip2022ext
972 Specifies that the extended IP2022 instructions are allowed.
973
974 -mip2022
975 Restores the default behaviour, which restricts the permitted
976 instructions to just the basic IP2022 ones.
977
978 The following options are available when as is configured for the
979 Renesas M32C and M16C processors.
980
981 -m32c
982 Assemble M32C instructions.
983
984 -m16c
985 Assemble M16C instructions (the default).
986
987 -relax
988 Enable support for link-time relaxations.
989
990 -h-tick-hex
991 Support H'00 style hex constants in addition to 0x00 style.
992
993 The following options are available when as is configured for the
994 Renesas M32R (formerly Mitsubishi M32R) series.
995
996 --m32rx
997 Specify which processor in the M32R family is the target. The
998 default is normally the M32R, but this option changes it to the
999 M32RX.
1000
1001 --warn-explicit-parallel-conflicts or --Wp
1002 Produce warning messages when questionable parallel constructs are
1003 encountered.
1004
1005 --no-warn-explicit-parallel-conflicts or --Wnp
1006 Do not produce warning messages when questionable parallel
1007 constructs are encountered.
1008
1009 The following options are available when as is configured for the
1010 Motorola 68000 series.
1011
1012 -l Shorten references to undefined symbols, to one word instead of
1013 two.
1014
1015 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1016 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1017 | -m68333 | -m68340 | -mcpu32 | -m5200
1018 Specify what processor in the 68000 family is the target. The
1019 default is normally the 68020, but this can be changed at
1020 configuration time.
1021
1022 -m68881 | -m68882 | -mno-68881 | -mno-68882
1023 The target machine does (or does not) have a floating-point
1024 coprocessor. The default is to assume a coprocessor for 68020,
1025 68030, and cpu32. Although the basic 68000 is not compatible with
1026 the 68881, a combination of the two can be specified, since it's
1027 possible to do emulation of the coprocessor instructions with the
1028 main processor.
1029
1030 -m68851 | -mno-68851
1031 The target machine does (or does not) have a memory-management unit
1032 coprocessor. The default is to assume an MMU for 68020 and up.
1033
1034 The following options are available when as is configured for an Altera
1035 Nios II processor.
1036
1037 -relax-section
1038 Replace identified out-of-range branches with PC-relative "jmp"
1039 sequences when possible. The generated code sequences are suitable
1040 for use in position-independent code, but there is a practical
1041 limit on the extended branch range because of the length of the
1042 sequences. This option is the default.
1043
1044 -relax-all
1045 Replace branch instructions not determinable to be in range and all
1046 call instructions with "jmp" and "callr" sequences (respectively).
1047 This option generates absolute relocations against the target
1048 symbols and is not appropriate for position-independent code.
1049
1050 -no-relax
1051 Do not replace any branches or calls.
1052
1053 -EB Generate big-endian output.
1054
1055 -EL Generate little-endian output. This is the default.
1056
1057 -march=architecture
1058 This option specifies the target architecture. The assembler
1059 issues an error message if an attempt is made to assemble an
1060 instruction which will not execute on the target architecture. The
1061 following architecture names are recognized: "r1", "r2". The
1062 default is "r1".
1063
1064 The following options are available when as is configured for a Meta
1065 processor.
1066
1067 "-mcpu=metac11"
1068 Generate code for Meta 1.1.
1069
1070 "-mcpu=metac12"
1071 Generate code for Meta 1.2.
1072
1073 "-mcpu=metac21"
1074 Generate code for Meta 2.1.
1075
1076 "-mfpu=metac21"
1077 Allow code to use FPU hardware of Meta 2.1.
1078
1079 See the info pages for documentation of the MMIX-specific options.
1080
1081 The following options are available when as is configured for a NDS32
1082 processor.
1083
1084 "-O1"
1085 Optimize for performance.
1086
1087 "-Os"
1088 Optimize for space.
1089
1090 "-EL"
1091 Produce little endian data output.
1092
1093 "-EB"
1094 Produce little endian data output.
1095
1096 "-mpic"
1097 Generate PIC.
1098
1099 "-mno-fp-as-gp-relax"
1100 Suppress fp-as-gp relaxation for this file.
1101
1102 "-mb2bb-relax"
1103 Back-to-back branch optimization.
1104
1105 "-mno-all-relax"
1106 Suppress all relaxation for this file.
1107
1108 "-march=<arch name>"
1109 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1110 v3f, v3s, v2, v2j, v2f, v2s.
1111
1112 "-mbaseline=<baseline>"
1113 Assemble for baseline <baseline> which could be v2, v3, v3m.
1114
1115 "-mfpu-freg=FREG"
1116 Specify a FPU configuration.
1117
1118 "0 8 SP / 4 DP registers"
1119 "1 16 SP / 8 DP registers"
1120 "2 32 SP / 16 DP registers"
1121 "3 32 SP / 32 DP registers"
1122 "-mabi=abi"
1123 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1124
1125 "-m[no-]mac"
1126 Enable/Disable Multiply instructions support.
1127
1128 "-m[no-]div"
1129 Enable/Disable Divide instructions support.
1130
1131 "-m[no-]16bit-ext"
1132 Enable/Disable 16-bit extension
1133
1134 "-m[no-]dx-regs"
1135 Enable/Disable d0/d1 registers
1136
1137 "-m[no-]perf-ext"
1138 Enable/Disable Performance extension
1139
1140 "-m[no-]perf2-ext"
1141 Enable/Disable Performance extension 2
1142
1143 "-m[no-]string-ext"
1144 Enable/Disable String extension
1145
1146 "-m[no-]reduced-regs"
1147 Enable/Disable Reduced Register configuration (GPR16) option
1148
1149 "-m[no-]audio-isa-ext"
1150 Enable/Disable AUDIO ISA extension
1151
1152 "-m[no-]fpu-sp-ext"
1153 Enable/Disable FPU SP extension
1154
1155 "-m[no-]fpu-dp-ext"
1156 Enable/Disable FPU DP extension
1157
1158 "-m[no-]fpu-fma"
1159 Enable/Disable FPU fused-multiply-add instructions
1160
1161 "-mall-ext"
1162 Turn on all extensions and instructions support
1163
1164 The following options are available when as is configured for a PowerPC
1165 processor.
1166
1167 -a32
1168 Generate ELF32 or XCOFF32.
1169
1170 -a64
1171 Generate ELF64 or XCOFF64.
1172
1173 -K PIC
1174 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1175
1176 -mpwrx | -mpwr2
1177 Generate code for POWER/2 (RIOS2).
1178
1179 -mpwr
1180 Generate code for POWER (RIOS1)
1181
1182 -m601
1183 Generate code for PowerPC 601.
1184
1185 -mppc, -mppc32, -m603, -m604
1186 Generate code for PowerPC 603/604.
1187
1188 -m403, -m405
1189 Generate code for PowerPC 403/405.
1190
1191 -m440
1192 Generate code for PowerPC 440. BookE and some 405 instructions.
1193
1194 -m464
1195 Generate code for PowerPC 464.
1196
1197 -m476
1198 Generate code for PowerPC 476.
1199
1200 -m7400, -m7410, -m7450, -m7455
1201 Generate code for PowerPC 7400/7410/7450/7455.
1202
1203 -m750cl
1204 Generate code for PowerPC 750CL.
1205
1206 -m821, -m850, -m860
1207 Generate code for PowerPC 821/850/860.
1208
1209 -mppc64, -m620
1210 Generate code for PowerPC 620/625/630.
1211
1212 -me500, -me500x2
1213 Generate code for Motorola e500 core complex.
1214
1215 -me500mc
1216 Generate code for Freescale e500mc core complex.
1217
1218 -me500mc64
1219 Generate code for Freescale e500mc64 core complex.
1220
1221 -me5500
1222 Generate code for Freescale e5500 core complex.
1223
1224 -me6500
1225 Generate code for Freescale e6500 core complex.
1226
1227 -mspe
1228 Generate code for Motorola SPE instructions.
1229
1230 -mtitan
1231 Generate code for AppliedMicro Titan core complex.
1232
1233 -mppc64bridge
1234 Generate code for PowerPC 64, including bridge insns.
1235
1236 -mbooke
1237 Generate code for 32-bit BookE.
1238
1239 -ma2
1240 Generate code for A2 architecture.
1241
1242 -me300
1243 Generate code for PowerPC e300 family.
1244
1245 -maltivec
1246 Generate code for processors with AltiVec instructions.
1247
1248 -mvle
1249 Generate code for Freescale PowerPC VLE instructions.
1250
1251 -mvsx
1252 Generate code for processors with Vector-Scalar (VSX) instructions.
1253
1254 -mhtm
1255 Generate code for processors with Hardware Transactional Memory
1256 instructions.
1257
1258 -mpower4, -mpwr4
1259 Generate code for Power4 architecture.
1260
1261 -mpower5, -mpwr5, -mpwr5x
1262 Generate code for Power5 architecture.
1263
1264 -mpower6, -mpwr6
1265 Generate code for Power6 architecture.
1266
1267 -mpower7, -mpwr7
1268 Generate code for Power7 architecture.
1269
1270 -mpower8, -mpwr8
1271 Generate code for Power8 architecture.
1272
1273 -mpower9, -mpwr9
1274 Generate code for Power9 architecture.
1275
1276 -mcell
1277 -mcell
1278 Generate code for Cell Broadband Engine architecture.
1279
1280 -mcom
1281 Generate code Power/PowerPC common instructions.
1282
1283 -many
1284 Generate code for any architecture (PWR/PWRX/PPC).
1285
1286 -mregnames
1287 Allow symbolic names for registers.
1288
1289 -mno-regnames
1290 Do not allow symbolic names for registers.
1291
1292 -mrelocatable
1293 Support for GCC's -mrelocatable option.
1294
1295 -mrelocatable-lib
1296 Support for GCC's -mrelocatable-lib option.
1297
1298 -memb
1299 Set PPC_EMB bit in ELF flags.
1300
1301 -mlittle, -mlittle-endian, -le
1302 Generate code for a little endian machine.
1303
1304 -mbig, -mbig-endian, -be
1305 Generate code for a big endian machine.
1306
1307 -msolaris
1308 Generate code for Solaris.
1309
1310 -mno-solaris
1311 Do not generate code for Solaris.
1312
1313 -nops=count
1314 If an alignment directive inserts more than count nops, put a
1315 branch at the beginning to skip execution of the nops.
1316
1317 See the info pages for documentation of the RX-specific options.
1318
1319 The following options are available when as is configured for the s390
1320 processor family.
1321
1322 -m31
1323 -m64
1324 Select the word size, either 31/32 bits or 64 bits.
1325
1326 -mesa
1327 -mzarch
1328 Select the architecture mode, either the Enterprise System
1329 Architecture (esa) or the z/Architecture mode (zarch).
1330
1331 -march=processor
1332 Specify which s390 processor variant is the target, g6, g6, z900,
1333 z990, z9-109, z9-ec, z10, z196, zEC12, or z13 (or arch11), or
1334 arch12.
1335
1336 -mregnames
1337 -mno-regnames
1338 Allow or disallow symbolic names for registers.
1339
1340 -mwarn-areg-zero
1341 Warn whenever the operand for a base or index register has been
1342 specified but evaluates to zero.
1343
1344 The following options are available when as is configured for a
1345 TMS320C6000 processor.
1346
1347 -march=arch
1348 Enable (only) instructions from architecture arch. By default, all
1349 instructions are permitted.
1350
1351 The following values of arch are accepted: "c62x", "c64x", "c64x+",
1352 "c67x", "c67x+", "c674x".
1353
1354 -mdsbt
1355 -mno-dsbt
1356 The -mdsbt option causes the assembler to generate the
1357 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1358 code is using DSBT addressing. The -mno-dsbt option, the default,
1359 causes the tag to have a value of 0, indicating that the code does
1360 not use DSBT addressing. The linker will emit a warning if objects
1361 of different type (DSBT and non-DSBT) are linked together.
1362
1363 -mpid=no
1364 -mpid=near
1365 -mpid=far
1366 The -mpid= option causes the assembler to generate the
1367 "Tag_ABI_PID" attribute with a value indicating the form of data
1368 addressing used by the code. -mpid=no, the default, indicates
1369 position-dependent data addressing, -mpid=near indicates position-
1370 independent addressing with GOT accesses using near DP addressing,
1371 and -mpid=far indicates position-independent addressing with GOT
1372 accesses using far DP addressing. The linker will emit a warning
1373 if objects built with different settings of this option are linked
1374 together.
1375
1376 -mpic
1377 -mno-pic
1378 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1379 attribute with a value of 1, indicating that the code is using
1380 position-independent code addressing, The "-mno-pic" option, the
1381 default, causes the tag to have a value of 0, indicating position-
1382 dependent code addressing. The linker will emit a warning if
1383 objects of different type (position-dependent and position-
1384 independent) are linked together.
1385
1386 -mbig-endian
1387 -mlittle-endian
1388 Generate code for the specified endianness. The default is little-
1389 endian.
1390
1391 The following options are available when as is configured for a TILE-Gx
1392 processor.
1393
1394 -m32 | -m64
1395 Select the word size, either 32 bits or 64 bits.
1396
1397 -EB | -EL
1398 Select the endianness, either big-endian (-EB) or little-endian
1399 (-EL).
1400
1401 The following option is available when as is configured for a Visium
1402 processor.
1403
1404 -mtune=arch
1405 This option specifies the target architecture. If an attempt is
1406 made to assemble an instruction that will not execute on the target
1407 architecture, the assembler will issue an error message.
1408
1409 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1410
1411 The following options are available when as is configured for an Xtensa
1412 processor.
1413
1414 --text-section-literals | --no-text-section-literals
1415 Control the treatment of literal pools. The default is
1416 --no-text-section-literals, which places literals in separate
1417 sections in the output file. This allows the literal pool to be
1418 placed in a data RAM/ROM. With --text-section-literals, the
1419 literals are interspersed in the text section in order to keep them
1420 as close as possible to their references. This may be necessary
1421 for large assembly files, where the literals would otherwise be out
1422 of range of the "L32R" instructions in the text section. Literals
1423 are grouped into pools following ".literal_position" directives or
1424 preceding "ENTRY" instructions. These options only affect literals
1425 referenced via PC-relative "L32R" instructions; literals for
1426 absolute mode "L32R" instructions are handled separately.
1427
1428 --auto-litpools | --no-auto-litpools
1429 Control the treatment of literal pools. The default is
1430 --no-auto-litpools, which in the absence of --text-section-literals
1431 places literals in separate sections in the output file. This
1432 allows the literal pool to be placed in a data RAM/ROM. With
1433 --auto-litpools, the literals are interspersed in the text section
1434 in order to keep them as close as possible to their references,
1435 explicit ".literal_position" directives are not required. This may
1436 be necessary for very large functions, where single literal pool at
1437 the beginning of the function may not be reachable by "L32R"
1438 instructions at the end. These options only affect literals
1439 referenced via PC-relative "L32R" instructions; literals for
1440 absolute mode "L32R" instructions are handled separately. When
1441 used together with --text-section-literals, --auto-litpools takes
1442 precedence.
1443
1444 --absolute-literals | --no-absolute-literals
1445 Indicate to the assembler whether "L32R" instructions use absolute
1446 or PC-relative addressing. If the processor includes the absolute
1447 addressing option, the default is to use absolute "L32R"
1448 relocations. Otherwise, only the PC-relative "L32R" relocations
1449 can be used.
1450
1451 --target-align | --no-target-align
1452 Enable or disable automatic alignment to reduce branch penalties at
1453 some expense in code size. This optimization is enabled by
1454 default. Note that the assembler will always align instructions
1455 like "LOOP" that have fixed alignment requirements.
1456
1457 --longcalls | --no-longcalls
1458 Enable or disable transformation of call instructions to allow
1459 calls across a greater range of addresses. This option should be
1460 used when call targets can potentially be out of range. It may
1461 degrade both code size and performance, but the linker can
1462 generally optimize away the unnecessary overhead when a call ends
1463 up within range. The default is --no-longcalls.
1464
1465 --transform | --no-transform
1466 Enable or disable all assembler transformations of Xtensa
1467 instructions, including both relaxation and optimization. The
1468 default is --transform; --no-transform should only be used in the
1469 rare cases when the instructions must be exactly as specified in
1470 the assembly source. Using --no-transform causes out of range
1471 instruction operands to be errors.
1472
1473 --rename-section oldname=newname
1474 Rename the oldname section to newname. This option can be used
1475 multiple times to rename multiple sections.
1476
1477 --trampolines | --no-trampolines
1478 Enable or disable transformation of jump instructions to allow
1479 jumps across a greater range of addresses. This option should be
1480 used when jump targets can potentially be out of range. In the
1481 absence of such jumps this option does not affect code size or
1482 performance. The default is --trampolines.
1483
1484 The following options are available when as is configured for a Z80
1485 family processor.
1486
1487 -z80
1488 Assemble for Z80 processor.
1489
1490 -r800
1491 Assemble for R800 processor.
1492
1493 -ignore-undocumented-instructions
1494 -Wnud
1495 Assemble undocumented Z80 instructions that also work on R800
1496 without warning.
1497
1498 -ignore-unportable-instructions
1499 -Wnup
1500 Assemble all undocumented Z80 instructions without warning.
1501
1502 -warn-undocumented-instructions
1503 -Wud
1504 Issue a warning for undocumented Z80 instructions that also work on
1505 R800.
1506
1507 -warn-unportable-instructions
1508 -Wup
1509 Issue a warning for undocumented Z80 instructions that do not work
1510 on R800.
1511
1512 -forbid-undocumented-instructions
1513 -Fud
1514 Treat all undocumented instructions as errors.
1515
1516 -forbid-unportable-instructions
1517 -Fup
1518 Treat undocumented Z80 instructions that do not work on R800 as
1519 errors.
1520
1522 gcc(1), ld(1), and the Info entries for binutils and ld.
1523
1525 Copyright (c) 1991-2016 Free Software Foundation, Inc.
1526
1527 Permission is granted to copy, distribute and/or modify this document
1528 under the terms of the GNU Free Documentation License, Version 1.3 or
1529 any later version published by the Free Software Foundation; with no
1530 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1531 Texts. A copy of the license is included in the section entitled "GNU
1532 Free Documentation License".
1533
1534
1535
1536binutils-2.27 2018-10-30 AS(1)