1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-<N>] [--gdwarf-sections]
14 [--gdwarf-cie-version=VERSION]
15 [--help] [-I dir] [-J]
16 [-K] [-L] [--listing-lhs-width=NUM]
17 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18 [--listing-cont-lines=NUM] [--keep-locals]
19 [--no-pad-sections]
20 [-o objfile] [-R]
21 [--statistics]
22 [-v] [-version] [--version]
23 [-W] [--warn] [--fatal-warnings] [-w] [-x]
24 [-Z] [@FILE]
25 [--sectname-subst] [--size-check=[error|warning]]
26 [--elf-stt-common=[no|yes]]
27 [--generate-missing-build-notes=[no|yes]]
28 [--target-help] [target-options]
29 [--|files ...]
30
32 Target AArch64 options:
33 [-EB|-EL]
34 [-mabi=ABI]
35 Target Alpha options:
37 [-mcpu]
38 [-mdebug | -no-mdebug]
39 [-replace | -noreplace]
40 [-relax] [-g] [-Gsize]
41 [-F] [-32addr]
42 Target ARC options:
44 [-mcpu=cpu]
45 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
46 [-mcode-density]
47 [-mrelax]
48 [-EB|-EL]
49 Target ARM options:
51 [-mcpu=processor[+extension...]]
52 [-march=architecture[+extension...]]
53 [-mfpu=floating-point-format]
54 [-mfloat-abi=abi]
55 [-meabi=ver]
56 [-mthumb]
57 [-EB|-EL]
58 [-mapcs-32|-mapcs-26|-mapcs-float|
59 -mapcs-reentrant]
60 [-mthumb-interwork] [-k]
61 Target Blackfin options:
63 [-mcpu=processor[-sirevision]]
64 [-mfdpic]
65 [-mno-fdpic]
66 [-mnopic]
67 Target BPF options:
69 [-EL] [-EB]
70 Target CRIS options:
72 [--underscore | --no-underscore]
73 [--pic] [-N]
74 [--emulation=criself | --emulation=crisaout]
75 [--march=v0_v10 | --march=v10 | --march=v32 |
76 --march=common_v10_v32]
77 Target C-SKY options:
79 [-march=arch] [-mcpu=cpu]
80 [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
81 [-fpic] [-pic]
82 [-mljump] [-mno-ljump]
83 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
84 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
85 [-mnolrw ] [-mno-lrw]
86 [-melrw] [-mno-elrw]
87 [-mlaf ] [-mliterals-after-func]
88 [-mno-laf] [-mno-literals-after-func]
89 [-mlabr] [-mliterals-after-br]
90 [-mno-labr] [-mnoliterals-after-br]
91 [-mistack] [-mno-istack]
92 [-mhard-float] [-mmp] [-mcp] [-mcache]
93 [-msecurity] [-mtrust]
94 [-mdsp] [-medsp] [-mvdsp]
95 Target D10V options:
97 [-O]
98 Target D30V options:
100 [-O|-n|-N]
101 Target EPIPHANY options:
103 [-mepiphany|-mepiphany16]
104 Target H8/300 options:
106 [-h-tick-hex]
107 Target i386 options:
109 [--32|--x32|--64] [-n]
110 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
111 Target IA-64 options:
113 [-mconstant-gp|-mauto-pic]
114 [-milp32|-milp64|-mlp64|-mp64]
115 [-mle|mbe]
116 [-mtune=itanium1|-mtune=itanium2]
117 [-munwind-check=warning|-munwind-check=error]
118 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
119 [-x|-xexplicit] [-xauto] [-xdebug]
120 Target IP2K options:
122 [-mip2022|-mip2022ext]
123 Target M32C options:
125 [-m32c|-m16c] [-relax] [-h-tick-hex]
126 Target M32R options:
128 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
129 --W[n]p]
130 Target M680X0 options:
132 [-l] [-m68000|-m68010|-m68020|...]
133 Target M68HC11 options:
135 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
136 [-mshort|-mlong]
137 [-mshort-double|-mlong-double]
138 [--force-long-branches] [--short-branches]
139 [--strict-direct-mode] [--print-insn-syntax]
140 [--print-opcodes] [--generate-example]
141 Target MCORE options:
143 [-jsri2bsr] [-sifilter] [-relax]
144 [-mcpu=[210|340]]
145 Target Meta options:
147 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
148 Target MIPS options:
150 [-nocpp] [-EL] [-EB] [-O[optimization level]]
151 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
152 [-non_shared] [-xgot [-mvxworks-pic]
153 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
154 [-mfp64] [-mgp64] [-mfpxx]
155 [-modd-spreg] [-mno-odd-spreg]
156 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
157 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
158 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
159 [-mips64r3] [-mips64r5] [-mips64r6]
160 [-construct-floats] [-no-construct-floats]
161 [-mignore-branch-isa] [-mno-ignore-branch-isa]
162 [-mnan=encoding]
163 [-trap] [-no-break] [-break] [-no-trap]
164 [-mips16] [-no-mips16]
165 [-mmips16e2] [-mno-mips16e2]
166 [-mmicromips] [-mno-micromips]
167 [-msmartmips] [-mno-smartmips]
168 [-mips3d] [-no-mips3d]
169 [-mdmx] [-no-mdmx]
170 [-mdsp] [-mno-dsp]
171 [-mdspr2] [-mno-dspr2]
172 [-mdspr3] [-mno-dspr3]
173 [-mmsa] [-mno-msa]
174 [-mxpa] [-mno-xpa]
175 [-mmt] [-mno-mt]
176 [-mmcu] [-mno-mcu]
177 [-mcrc] [-mno-crc]
178 [-mginv] [-mno-ginv]
179 [-mloongson-mmi] [-mno-loongson-mmi]
180 [-mloongson-cam] [-mno-loongson-cam]
181 [-mloongson-ext] [-mno-loongson-ext]
182 [-mloongson-ext2] [-mno-loongson-ext2]
183 [-minsn32] [-mno-insn32]
184 [-mfix7000] [-mno-fix7000]
185 [-mfix-rm7000] [-mno-fix-rm7000]
186 [-mfix-vr4120] [-mno-fix-vr4120]
187 [-mfix-vr4130] [-mno-fix-vr4130]
188 [-mfix-r5900] [-mno-fix-r5900]
189 [-mdebug] [-no-mdebug]
190 [-mpdr] [-mno-pdr]
191 Target MMIX options:
193 [--fixed-special-register-names] [--globalize-symbols]
194 [--gnu-syntax] [--relax] [--no-predefined-symbols]
195 [--no-expand] [--no-merge-gregs] [-x]
196 [--linker-allocated-gregs]
197 Target Nios II options:
199 [-relax-all] [-relax-section] [-no-relax]
200 [-EB] [-EL]
201 Target NDS32 options:
203 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
204 [-misa=isa] [-mabi=abi] [-mall-ext]
205 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
206 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
207 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
208 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
209 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
210 [-mb2bb]
211 Target PDP11 options:
213 [-mpic|-mno-pic] [-mall] [-mno-extensions]
214 [-mextension|-mno-extension]
215 [-mcpu] [-mmachine]
216 Target picoJava options:
218 [-mb|-me]
219 Target PowerPC options:
221 [-a32|-a64]
222 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
223 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
224 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
225 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
226 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
227 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
228 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
229 [-mregnames|-mno-regnames]
230 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
231 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
232 [-msolaris|-mno-solaris]
233 [-nops=count]
234 Target PRU options:
236 [-link-relax]
237 [-mnolink-relax]
238 [-mno-warn-regname-label]
239 Target RISC-V options:
241 [-fpic|-fPIC|-fno-pic]
242 [-march=ISA]
243 [-mabi=ABI]
244 [-mlittle-endian|-mbig-endian]
245 Target RL78 options:
247 [-mg10]
248 [-m32bit-doubles|-m64bit-doubles]
249 Target RX options:
251 [-mlittle-endian|-mbig-endian]
252 [-m32bit-doubles|-m64bit-doubles]
253 [-muse-conventional-section-names]
254 [-msmall-data-limit]
255 [-mpid]
256 [-mrelax]
257 [-mint-register=number]
258 [-mgcc-abi|-mrx-abi]
259 Target s390 options:
261 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
262 [-mregnames|-mno-regnames]
263 [-mwarn-areg-zero]
264 Target SCORE options:
266 [-EB][-EL][-FIXDD][-NWARN]
267 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
268 [-march=score7][-march=score3]
269 [-USE_R1][-KPIC][-O0][-G num][-V]
270 Target SPARC options:
272 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
273 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
274 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
275 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
276 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
277 -Asparcvisr|-Asparc5]
278 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
279 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
280 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
281 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
282 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
283 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
284 -bump]
285 [-32|-64]
286 [--enforce-aligned-data][--dcti-couples-detect]
287 Target TIC54X options:
289 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
290 [-merrors-to-file <filename>|-me <filename>]
291 Target TIC6X options:
293 [-march=arch] [-mbig-endian|-mlittle-endian]
294 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
295 [-mpic|-mno-pic]
296 Target TILE-Gx options:
298 [-m32|-m64][-EB][-EL]
299 Target Visium options:
301 [-mtune=arch]
302 Target Xtensa options:
304 [--[no-]text-section-literals] [--[no-]auto-litpools]
305 [--[no-]absolute-literals]
306 [--[no-]target-align] [--[no-]longcalls]
307 [--[no-]transform]
308 [--rename-section oldname=newname]
309 [--[no-]trampolines]
310 [--abi-windowed|--abi-call0]
311 Target Z80 options:
313 [-march=CPU[-EXT][+EXT]]
314 [-local-prefix=PREFIX]
315 [-colonless]
316 [-sdcc]
317 [-fp-s=FORMAT]
318 [-fp-d=FORMAT]
319
321 GNU as is really a family of assemblers. If you use (or have used) the
322 GNU assembler on one architecture, you should find a fairly similar
323 environment when you use it on another architecture. Each version has
324 much in common with the others, including object file formats, most
325 assembler directives (often called pseudo-ops) and assembler syntax.
326 as is primarily intended to assemble the output of the GNU C compiler
328 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
329 assemble correctly everything that other assemblers for the same
330 machine would assemble. Any exceptions are documented explicitly.
331 This doesn't mean as always uses the same syntax as another assembler
332 for the same architecture; for example, we know of several incompatible
333 versions of 680x0 assembly language syntax.
334 Each time you run as it assembles exactly one source program. The
336 source program is made up of one or more files. (The standard input is
337 also a file.)
338 You give as a command line that has zero or more input file names. The
340 input files are read (from left file name to right). A command-line
341 argument (in any position) that has no special meaning is taken to be
342 an input file name.
343 If you give as no file names it attempts to read one input file from
345 the as standard input, which is normally your terminal. You may have
346 to type ctl-D to tell as there is no more program to assemble.
347 Use -- if you need to explicitly name the standard input file in your
349 command line.
350 If the source is empty, as produces a small, empty object file.
352 as may write warnings and error messages to the standard error file
354 (usually your terminal). This should not happen when a compiler runs
355 as automatically. Warnings report an assumption made so that as could
356 keep assembling a flawed program; errors report a grave problem that
357 stops the assembly.
358 If you are invoking as via the GNU C compiler, you can use the -Wa
360 option to pass arguments through to the assembler. The assembler
361 arguments must be separated from each other (and the -Wa) by commas.
362 For example:
363 gcc -c -g -O -Wa,-alh,-L file.c
365 This passes two options to the assembler: -alh (emit a listing to
367 standard output with high-level and assembly source) and -L (retain
368 local symbols in the symbol table).
369 Usually you do not need to use this -Wa mechanism, since many compiler
371 command-line options are automatically passed to the assembler by the
372 compiler. (You can call the GNU compiler driver with the -v option to
373 see precisely what options it passes to each compilation pass,
374 including the assembler.)
375
377 @file
378 Read command-line options from file. The options read are inserted
379 in place of the original @file option. If file does not exist, or
380 cannot be read, then the option will be treated literally, and not
381 removed.
382 Options in file are separated by whitespace. A whitespace
384 character may be included in an option by surrounding the entire
385 option in either single or double quotes. Any character (including
386 a backslash) may be included by prefixing the character to be
387 included with a backslash. The file may itself contain additional
388 @file options; any such options will be processed recursively.
389 -a[cdghlmns]
391 Turn on listings, in any of a variety of ways:
392 -ac omit false conditionals
394 -ad omit debugging directives
396 -ag include general information, like as version and options passed
398 -ah include high-level source
400 -al include assembly
402 -am include macro expansions
404 -an omit forms processing
406 -as include symbols
408 =file
410 set the name of the listing file
411 You may combine these options; for example, use -aln for assembly
413 listing without forms processing. The =file option, if used, must
414 be the last one. By itself, -a defaults to -ahls.
415 --alternate
417 Begin in alternate macro mode.
418 --compress-debug-sections
420 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
421 the ELF ABI. The resulting object file may not be compatible with
422 older linkers and object file utilities. Note if compression would
423 make a given section larger then it is not compressed.
424 --compress-debug-sections=none
426 --compress-debug-sections=zlib
427 --compress-debug-sections=zlib-gnu
428 --compress-debug-sections=zlib-gabi
429 These options control how DWARF debug sections are compressed.
430 --compress-debug-sections=none is equivalent to
431 --nocompress-debug-sections. --compress-debug-sections=zlib and
432 --compress-debug-sections=zlib-gabi are equivalent to
433 --compress-debug-sections. --compress-debug-sections=zlib-gnu
434 compresses DWARF debug sections using zlib. The debug sections are
435 renamed to begin with .zdebug. Note if compression would make a
436 given section larger then it is not compressed nor renamed.
437 --nocompress-debug-sections
439 Do not compress DWARF debug sections. This is usually the default
440 for all targets except the x86/x86_64, but a configure time option
441 can be used to override this.
442 -D Ignored. This option is accepted for script compatibility with
444 calls to other assemblers.
445 --debug-prefix-map old=new
447 When assembling files in directory old, record debugging
448 information describing them as in new instead.
449 --defsym sym=value
451 Define the symbol sym to be value before assembling the input file.
452 value must be an integer constant. As in C, a leading 0x indicates
453 a hexadecimal value, and a leading 0 indicates an octal value. The
454 value of the symbol can be overridden inside a source file via the
455 use of a ".set" pseudo-op.
456 -f "fast"---skip whitespace and comment preprocessing (assume source
458 is compiler output).
459 -g
461 --gen-debug
462 Generate debugging information for each assembler source line using
463 whichever debug format is preferred by the target. This currently
464 means either STABS, ECOFF or DWARF2. When the debug format is
465 DWARF then a ".debug_info" and ".debug_line" section is only
466 emitted when the assembly file doesn't generate one itself.
467 --gstabs
469 Generate stabs debugging information for each assembler line. This
470 may help debugging assembler code, if the debugger can handle it.
471 --gstabs+
473 Generate stabs debugging information for each assembler line, with
474 GNU extensions that probably only gdb can handle, and that could
475 make other debuggers crash or refuse to read your program. This
476 may help debugging assembler code. Currently the only GNU
477 extension is the location of the current working directory at
478 assembling time.
479 --gdwarf-2
481 Generate DWARF2 debugging information for each assembler line.
482 This may help debugging assembler code, if the debugger can handle
483 it. Note---this option is only supported by some targets, not all
484 of them.
485 --gdwarf-3
487 This option is the same as the --gdwarf-2 option, except that it
488 allows for the possibility of the generation of extra debug
489 information as per version 3 of the DWARF specification. Note -
490 enabling this option does not guarantee the generation of any extra
491 information, the choice to do so is on a per target basis.
492 --gdwarf-4
494 This option is the same as the --gdwarf-2 option, except that it
495 allows for the possibility of the generation of extra debug
496 information as per version 4 of the DWARF specification. Note -
497 enabling this option does not guarantee the generation of any extra
498 information, the choice to do so is on a per target basis.
499 --gdwarf-5
501 This option is the same as the --gdwarf-2 option, except that it
502 allows for the possibility of the generation of extra debug
503 information as per version 5 of the DWARF specification. Note -
504 enabling this option does not guarantee the generation of any extra
505 information, the choice to do so is on a per target basis.
506 --gdwarf-sections
508 Instead of creating a .debug_line section, create a series of
509 .debug_line.foo sections where foo is the name of the corresponding
510 code section. For example a code section called .text.func will
511 have its dwarf line number information placed into a section called
512 .debug_line.text.func. If the code section is just called .text
513 then debug line section will still be called just .debug_line
514 without any suffix.
515 --gdwarf-cie-version=version
517 Control which version of DWARF Common Information Entries (CIEs)
518 are produced. When this flag is not specificed the default is
519 version 1, though some targets can modify this default. Other
520 possible values for version are 3 or 4.
521 --size-check=error
523 --size-check=warning
524 Issue an error or warning for invalid ELF .size directive.
525 --elf-stt-common=no
527 --elf-stt-common=yes
528 These options control whether the ELF assembler should generate
529 common symbols with the "STT_COMMON" type. The default can be
530 controlled by a configure option --enable-elf-stt-common.
531 --generate-missing-build-notes=yes
533 --generate-missing-build-notes=no
534 These options control whether the ELF assembler should generate GNU
535 Build attribute notes if none are present in the input sources.
536 The default can be controlled by the --enable-generate-build-notes
537 configure option.
538 --help
540 Print a summary of the command-line options and exit.
541 --target-help
543 Print a summary of all target specific options and exit.
544 -I dir
546 Add directory dir to the search list for ".include" directives.
547 -J Don't warn about signed overflow.
549 -K Issue warnings when difference tables altered for long
551 displacements.
552 -L
554 --keep-locals
555 Keep (in the symbol table) local symbols. These symbols start with
556 system-specific local label prefixes, typically .L for ELF systems
557 or L for traditional a.out systems.
558 --listing-lhs-width=number
560 Set the maximum width, in words, of the output data column for an
561 assembler listing to number.
562 --listing-lhs-width2=number
564 Set the maximum width, in words, of the output data column for
565 continuation lines in an assembler listing to number.
566 --listing-rhs-width=number
568 Set the maximum width of an input source line, as displayed in a
569 listing, to number bytes.
570 --listing-cont-lines=number
572 Set the maximum number of lines printed in a listing for a single
573 line of input to number + 1.
574 --no-pad-sections
576 Stop the assembler for padding the ends of output sections to the
577 alignment of that section. The default is to pad the sections, but
578 this can waste space which might be needed on targets which have
579 tight memory constraints.
580 -o objfile
582 Name the object-file output from as objfile.
583 -R Fold the data section into the text section.
585 --sectname-subst
587 Honor substitution sequences in section names.
588 --statistics
590 Print the maximum space (in bytes) and total time (in seconds) used
591 by assembly.
592 --strip-local-absolute
594 Remove local absolute symbols from the outgoing symbol table.
595 -v
597 -version
598 Print the as version.
599 --version
601 Print the as version and exit.
602 -W
604 --no-warn
605 Suppress warning messages.
606 --fatal-warnings
608 Treat warnings as errors.
609 --warn
611 Don't suppress warning messages or treat them as errors.
612 -w Ignored.
614 -x Ignored.
616 -Z Generate an object file even after errors.
618 -- | files ...
620 Standard input, or source files to assemble.
621 The following options are available when as is configured for the
623 64-bit mode of the ARM Architecture (AArch64).
624 -EB This option specifies that the output generated by the assembler
626 should be marked as being encoded for a big-endian processor.
627 -EL This option specifies that the output generated by the assembler
629 should be marked as being encoded for a little-endian processor.
630 -mabi=abi
632 Specify which ABI the source code uses. The recognized arguments
633 are: "ilp32" and "lp64", which decides the generated object file in
634 ELF32 and ELF64 format respectively. The default is "lp64".
635 -mcpu=processor[+extension...]
637 This option specifies the target processor. The assembler will
638 issue an error message if an attempt is made to assemble an
639 instruction which will not execute on the target processor. The
640 following processor names are recognized: "cortex-a34",
641 "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
642 "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
643 "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77",
644 "cortex-a78", "cortex-a78ae", "cortex-a78c", "ares", "exynos-m1",
645 "falkor", "neoverse-n1", "neoverse-n2", "neoverse-e1",
646 "neoverse-v1", "qdf24xx", "saphira", "thunderx", "vulcan", "xgene1"
647 "xgene2", "cortex-r82", and "cortex-x1". The special name "all"
648 may be used to allow the assembler to accept instructions valid for
649 any supported processor, including all optional extensions.
650 In addition to the basic instruction set, the assembler can be told
652 to accept, or restrict, various extension mnemonics that extend the
653 processor.
654 If some implementations of a particular processor can have an
656 extension, then then those extensions are automatically enabled.
657 Consequently, you will not normally have to specify any additional
658 extensions.
659 -march=architecture[+extension...]
661 This option specifies the target architecture. The assembler will
662 issue an error message if an attempt is made to assemble an
663 instruction which will not execute on the target architecture. The
664 following architecture names are recognized: "armv8-a",
665 "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a",
666 "armv8.6-a", "armv8.7-a", and "armv8-r".
667 If both -mcpu and -march are specified, the assembler will use the
669 setting for -mcpu. If neither are specified, the assembler will
670 default to -mcpu=all.
671 The architecture option can be extended with the same instruction
673 set extension options as the -mcpu option. Unlike -mcpu,
674 extensions are not always enabled by default,
675 -mverbose-error
677 This option enables verbose error messages for AArch64 gas. This
678 option is enabled by default.
679 -mno-verbose-error
681 This option disables verbose error messages in AArch64 gas.
682 The following options are available when as is configured for an Alpha
684 processor.
685 -mcpu
687 This option specifies the target processor. If an attempt is made
688 to assemble an instruction which will not execute on the target
689 processor, the assembler may either expand the instruction as a
690 macro or issue an error message. This option is equivalent to the
691 ".arch" directive.
692 The following processor names are recognized: 21064, "21064a",
694 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
695 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
696 "ev67", "ev68". The special name "all" may be used to allow the
697 assembler to accept instructions valid for any Alpha processor.
698 In order to support existing practice in OSF/1 with respect to
700 ".arch", and existing practice within MILO (the Linux ARC
701 bootloader), the numbered processor names (e.g. 21064) enable the
702 processor-specific PALcode instructions, while the "electro-vlasic"
703 names (e.g. "ev4") do not.
704 -mdebug
706 -no-mdebug
707 Enables or disables the generation of ".mdebug" encapsulation for
708 stabs directives and procedure descriptors. The default is to
709 automatically enable ".mdebug" when the first stabs directive is
710 seen.
711 -relax
713 This option forces all relocations to be put into the object file,
714 instead of saving space and resolving some relocations at assembly
715 time. Note that this option does not propagate all symbol
716 arithmetic into the object file, because not all symbol arithmetic
717 can be represented. However, the option can still be useful in
718 specific applications.
719 -replace
721 -noreplace
722 Enables or disables the optimization of procedure calls, both at
723 assemblage and at link time. These options are only available for
724 VMS targets and "-replace" is the default. See section 1.4.1 of
725 the OpenVMS Linker Utility Manual.
726 -g This option is used when the compiler generates debug information.
728 When gcc is using mips-tfile to generate debug information for
729 ECOFF, local labels must be passed through to the object file.
730 Otherwise this option has no effect.
731 -Gsize
733 A local common symbol larger than size is placed in ".bss", while
734 smaller symbols are placed in ".sbss".
735 -F
737 -32addr
738 These options are ignored for backward compatibility.
739 The following options are available when as is configured for an ARC
741 processor.
742 -mcpu=cpu
744 This option selects the core processor variant.
745 -EB | -EL
747 Select either big-endian (-EB) or little-endian (-EL) output.
748 -mcode-density
750 Enable Code Density extension instructions.
751 The following options are available when as is configured for the ARM
753 processor family.
754 -mcpu=processor[+extension...]
756 Specify which ARM processor variant is the target.
757 -march=architecture[+extension...]
759 Specify which ARM architecture variant is used by the target.
760 -mfpu=floating-point-format
762 Select which Floating Point architecture is the target.
763 -mfloat-abi=abi
765 Select which floating point ABI is in use.
766 -mthumb
768 Enable Thumb only instruction decoding.
769 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
771 Select which procedure calling convention is in use.
772 -EB | -EL
774 Select either big-endian (-EB) or little-endian (-EL) output.
775 -mthumb-interwork
777 Specify that the code has been generated with interworking between
778 Thumb and ARM code in mind.
779 -mccs
781 Turns on CodeComposer Studio assembly syntax compatibility mode.
782 -k Specify that PIC code has been generated.
784 The following options are available when as is configured for the
786 Blackfin processor family.
787 -mcpu=processor[-sirevision]
789 This option specifies the target processor. The optional
790 sirevision is not used in assembler. It's here such that GCC can
791 easily pass down its "-mcpu=" option. The assembler will issue an
792 error message if an attempt is made to assemble an instruction
793 which will not execute on the target processor. The following
794 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
795 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
796 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
797 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
798 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
799 "bf549", "bf549m", "bf561", and "bf592".
800 -mfdpic
802 Assemble for the FDPIC ABI.
803 -mno-fdpic
805 -mnopic
806 Disable -mfdpic.
807 The following options are available when as is configured for the Linux
809 kernel BPF processor family.
810 @chapter BPF Dependent Features
812 Options
814 -EB This option specifies that the assembler should emit big-endian
815 eBPF.
816 -EL This option specifies that the assembler should emit little-endian
818 eBPF.
819 Note that if no endianness option is specified in the command line, the
821 host endianness is used. See the info pages for documentation of the
822 CRIS-specific options.
823 The following options are available when as is configured for the C-SKY
825 processor family.
826 -march=archname
828 Assemble for architecture archname. The --help option lists valid
829 values for archname.
830 -mcpu=cpuname
832 Assemble for architecture cpuname. The --help option lists valid
833 values for cpuname.
834 -EL
836 -mlittle-endian
837 Generate little-endian output.
838 -EB
840 -mbig-endian
841 Generate big-endian output.
842 -fpic
844 -pic
845 Generate position-independent code.
846 -mljump
848 -mno-ljump
849 Enable/disable transformation of the short branch instructions
850 "jbf", "jbt", and "jbr" to "jmpi". This option is for V2
851 processors only. It is ignored on CK801 and CK802 targets, which
852 do not support the "jmpi" instruction, and is enabled by default
853 for other processors.
854 -mbranch-stub
856 -mno-branch-stub
857 Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
858 instructions to the linker.
859 This option is only available for bare-metal C-SKY V2 ELF targets,
861 where it is enabled by default. It cannot be used in code that
862 will be dynamically linked against shared libraries.
863 -force2bsr
865 -mforce2bsr
866 -no-force2bsr
867 -mno-force2bsr
868 Enable/disable transformation of "jbsr" instructions to "bsr".
869 This option is always enabled (and -mno-force2bsr is ignored) for
870 CK801/CK802 targets. It is also always enabled when -mbranch-stub
871 is in effect.
872 -jsri2bsr
874 -mjsri2bsr
875 -no-jsri2bsr
876 -mno-jsri2bsr
877 Enable/disable transformation of "jsri" instructions to "bsr".
878 This option is enabled by default.
879 -mnolrw
881 -mno-lrw
882 Enable/disable transformation of "lrw" instructions into a
883 "movih"/"ori" pair.
884 -melrw
886 -mno-elrw
887 Enable/disable extended "lrw" instructions. This option is enabled
888 by default for CK800-series processors.
889 -mlaf
891 -mliterals-after-func
892 -mno-laf
893 -mno-literals-after-func
894 Enable/disable placement of literal pools after each function.
895 -mlabr
897 -mliterals-after-br
898 -mno-labr
899 -mnoliterals-after-br
900 Enable/disable placement of literal pools after unconditional
901 branches. This option is enabled by default.
902 -mistack
904 -mno-istack
905 Enable/disable interrupt stack instructions. This option is
906 enabled by default on CK801, CK802, and CK802 processors.
907 The following options explicitly enable certain optional instructions.
909 These features are also enabled implicitly by using "-mcpu=" to specify
910 a processor that supports it.
911 -mhard-float
913 Enable hard float instructions.
914 -mmp
916 Enable multiprocessor instructions.
917 -mcp
919 Enable coprocessor instructions.
920 -mcache
922 Enable cache prefetch instruction.
923 -msecurity
925 Enable C-SKY security instructions.
926 -mtrust
928 Enable C-SKY trust instructions.
929 -mdsp
931 Enable DSP instructions.
932 -medsp
934 Enable enhanced DSP instructions.
935 -mvdsp
937 Enable vector DSP instructions.
938 The following options are available when as is configured for an
940 Epiphany processor.
941 -mepiphany
943 Specifies that the both 32 and 16 bit instructions are allowed.
944 This is the default behavior.
945 -mepiphany16
947 Restricts the permitted instructions to just the 16 bit set.
948 The following options are available when as is configured for an H8/300
950 processor. @chapter H8/300 Dependent Features
951 Options
953 The Renesas H8/300 version of "as" has one machine-dependent option:
954 -h-tick-hex
956 Support H'00 style hex constants in addition to 0x00 style.
957 -mach=name
959 Sets the H8300 machine variant. The following machine names are
960 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
961 "h8300sxn".
962 The following options are available when as is configured for an i386
964 processor.
965 --32 | --x32 | --64
967 Select the word size, either 32 bits or 64 bits. --32 implies
968 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
969 architecture with 32-bit or 64-bit word-size respectively.
970 These options are only available with the ELF object file format,
972 and require that the necessary BFD support has been included (on a
973 32-bit platform you have to add --enable-64-bit-bfd to configure
974 enable 64-bit usage and use x86-64 as target platform).
975 -n By default, x86 GAS replaces multiple nop instructions used for
977 alignment within code sections with multi-byte nop instructions
978 such as leal 0(%esi,1),%esi. This switch disables the optimization
979 if a single byte nop (0x90) is explicitly specified as the fill
980 byte for alignment.
981 --divide
983 On SVR4-derived platforms, the character / is treated as a comment
984 character, which means that it cannot be used in expressions. The
985 --divide option turns / into a normal character. This does not
986 disable / at the beginning of a line starting a comment, or affect
987 using # for starting a comment.
988 -march=CPU[+EXTENSION...]
990 This option specifies the target processor. The assembler will
991 issue an error message if an attempt is made to assemble an
992 instruction which will not execute on the target processor. The
993 following processor names are recognized: "i8086", "i186", "i286",
994 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
995 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
996 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
997 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
998 "bdver3", "bdver4", "znver1", "znver2", "znver3", "btver1",
999 "btver2", "generic32" and "generic64".
1000 In addition to the basic instruction set, the assembler can be told
1002 to accept various extension mnemonics. For example,
1003 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
1004 following extensions are currently supported: 8087, 287, 387, 687,
1005 "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1006 "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1007 "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nosse4a",
1008 "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2",
1009 "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
1010 "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq",
1011 "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b",
1012 "enqcmd", "serialize", "tsxldtrk", "kl", "nokl", "widekl",
1013 "nowidekl", "hreset", "avx512f", "avx512cd", "avx512er",
1014 "avx512pf", "avx512vl", "avx512bw", "avx512dq", "avx512ifma",
1015 "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
1016 "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1017 "avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni",
1018 "noavx512f", "noavx512cd", "noavx512er", "noavx512pf",
1019 "noavx512vl", "noavx512bw", "noavx512dq", "noavx512ifma",
1020 "noavx512vbmi", "noavx512_4fmaps", "noavx512_4vnniw",
1021 "noavx512_vpopcntdq", "noavx512_vbmi2", "noavx512_vnni",
1022 "noavx512_bitalg", "noavx512_vp2intersect", "notdx",
1023 "noavx512_bf16", "noavx_vnni", "noenqcmd", "noserialize",
1024 "notsxldtrk", "amx_int8", "noamx_int8", "amx_bf16", "noamx_bf16",
1025 "amx_tile", "noamx_tile", "nouintr", "nohreset", "vmx", "vmfunc",
1026 "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul",
1027 "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept",
1028 "lzcnt", "popcnt", "hle", "rtm", "invpcid", "clflush", "mwaitx",
1029 "clzero", "wbnoinvd", "pconfig", "waitpkg", "uintr", "cldemote",
1030 "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop", "cx16",
1031 "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "snp",
1032 "invlpgb", "tlbsync", "svme" and "padlock". Note that rather than
1033 extending a basic instruction set, the extension mnemonics starting
1034 with "no" revoke the respective functionality.
1035 When the ".arch" directive is used with -march, the ".arch"
1037 directive will take precedent.
1038 -mtune=CPU
1040 This option specifies a processor to optimize for. When used in
1041 conjunction with the -march option, only instructions of the
1042 processor specified by the -march option will be generated.
1043 Valid CPU values are identical to the processor list of -march=CPU.
1045 -msse2avx
1047 This option specifies that the assembler should encode SSE
1048 instructions with VEX prefix.
1049 -msse-check=none
1051 -msse-check=warning
1052 -msse-check=error
1053 These options control if the assembler should check SSE
1054 instructions. -msse-check=none will make the assembler not to
1055 check SSE instructions, which is the default. -msse-check=warning
1056 will make the assembler issue a warning for any SSE instruction.
1057 -msse-check=error will make the assembler issue an error for any
1058 SSE instruction.
1059 -mavxscalar=128
1061 -mavxscalar=256
1062 These options control how the assembler should encode scalar AVX
1063 instructions. -mavxscalar=128 will encode scalar AVX instructions
1064 with 128bit vector length, which is the default. -mavxscalar=256
1065 will encode scalar AVX instructions with 256bit vector length.
1066 WARNING: Don't use this for production code - due to CPU errata the
1068 resulting code may not work on certain models.
1069 -mvexwig=0
1071 -mvexwig=1
1072 These options control how the assembler should encode VEX.W-ignored
1073 (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX
1074 instructions with vex.w = 0, which is the default. -mvexwig=1 will
1075 encode WIG EVEX instructions with vex.w = 1.
1076 WARNING: Don't use this for production code - due to CPU errata the
1078 resulting code may not work on certain models.
1079 -mevexlig=128
1081 -mevexlig=256
1082 -mevexlig=512
1083 These options control how the assembler should encode length-
1084 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
1085 EVEX instructions with 128bit vector length, which is the default.
1086 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1087 with 256bit and 512bit vector length, respectively.
1088 -mevexwig=0
1090 -mevexwig=1
1091 These options control how the assembler should encode w-ignored
1092 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
1093 instructions with evex.w = 0, which is the default. -mevexwig=1
1094 will encode WIG EVEX instructions with evex.w = 1.
1095 -mmnemonic=att
1097 -mmnemonic=intel
1098 This option specifies instruction mnemonic for matching
1099 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
1100 will take precedent.
1101 -msyntax=att
1103 -msyntax=intel
1104 This option specifies instruction syntax when processing
1105 instructions. The ".att_syntax" and ".intel_syntax" directives
1106 will take precedent.
1107 -mnaked-reg
1109 This option specifies that registers don't require a % prefix. The
1110 ".att_syntax" and ".intel_syntax" directives will take precedent.
1111 -madd-bnd-prefix
1113 This option forces the assembler to add BND prefix to all branches,
1114 even if such prefix was not explicitly specified in the source
1115 code.
1116 -mno-shared
1118 On ELF target, the assembler normally optimizes out non-PLT
1119 relocations against defined non-weak global branch targets with
1120 default visibility. The -mshared option tells the assembler to
1121 generate code which may go into a shared library where all non-weak
1122 global branch targets with default visibility can be preempted.
1123 The resulting code is slightly bigger. This option only affects
1124 the handling of branch instructions.
1125 -mbig-obj
1127 On PE/COFF target this option forces the use of big object file
1128 format, which allows more than 32768 sections.
1129 -momit-lock-prefix=no
1131 -momit-lock-prefix=yes
1132 These options control how the assembler should encode lock prefix.
1133 This option is intended as a workaround for processors, that fail
1134 on lock prefix. This option can only be safely used with single-
1135 core, single-thread computers -momit-lock-prefix=yes will omit all
1136 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
1137 usual, which is the default.
1138 -mfence-as-lock-add=no
1140 -mfence-as-lock-add=yes
1141 These options control how the assembler should encode lfence,
1142 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
1143 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1144 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
1145 encode lfence, mfence and sfence as usual, which is the default.
1146 -mrelax-relocations=no
1148 -mrelax-relocations=yes
1149 These options control whether the assembler should generate relax
1150 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1151 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1152 -mrelax-relocations=yes will generate relax relocations.
1153 -mrelax-relocations=no will not generate relax relocations. The
1154 default can be controlled by a configure option
1155 --enable-x86-relax-relocations.
1156 -malign-branch-boundary=NUM
1158 This option controls how the assembler should align branches with
1159 segment prefixes or NOP. NUM must be a power of 2. It should be 0
1160 or no less than 16. Branches will be aligned within NUM byte
1161 boundary. -malign-branch-boundary=0, which is the default, doesn't
1162 align branches.
1163 -malign-branch=TYPE[+TYPE...]
1165 This option specifies types of branches to align. TYPE is
1166 combination of jcc, which aligns conditional jumps, fused, which
1167 aligns fused conditional jumps, jmp, which aligns unconditional
1168 jumps, call which aligns calls, ret, which aligns rets, indirect,
1169 which aligns indirect jumps and calls. The default is
1170 -malign-branch=jcc+fused+jmp.
1171 -malign-branch-prefix-size=NUM
1173 This option specifies the maximum number of prefixes on an
1174 instruction to align branches. NUM should be between 0 and 5. The
1175 default NUM is 5.
1176 -mbranches-within-32B-boundaries
1178 This option aligns conditional jumps, fused conditional jumps and
1179 unconditional jumps within 32 byte boundary with up to 5 segment
1180 prefixes on an instruction. It is equivalent to
1181 -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1182 -malign-branch-prefix-size=5. The default doesn't align branches.
1183 -mlfence-after-load=no
1185 -mlfence-after-load=yes
1186 These options control whether the assembler should generate lfence
1187 after load instructions. -mlfence-after-load=yes will generate
1188 lfence. -mlfence-after-load=no will not generate lfence, which is
1189 the default.
1190 -mlfence-before-indirect-branch=none
1192 -mlfence-before-indirect-branch=all
1193 -mlfence-before-indirect-branch=register
1194 -mlfence-before-indirect-branch=memory
1195 These options control whether the assembler should generate lfence
1196 before indirect near branch instructions.
1197 -mlfence-before-indirect-branch=all will generate lfence before
1198 indirect near branch via register and issue a warning before
1199 indirect near branch via memory. It also implicitly sets
1200 -mlfence-before-ret=shl when there's no explicit
1201 -mlfence-before-ret=. -mlfence-before-indirect-branch=register
1202 will generate lfence before indirect near branch via register.
1203 -mlfence-before-indirect-branch=memory will issue a warning before
1204 indirect near branch via memory.
1205 -mlfence-before-indirect-branch=none will not generate lfence nor
1206 issue warning, which is the default. Note that lfence won't be
1207 generated before indirect near branch via register with
1208 -mlfence-after-load=yes since lfence will be generated after
1209 loading branch target register.
1210 -mlfence-before-ret=none
1212 -mlfence-before-ret=shl
1213 -mlfence-before-ret=or
1214 -mlfence-before-ret=yes
1215 -mlfence-before-ret=not
1216 These options control whether the assembler should generate lfence
1217 before ret. -mlfence-before-ret=or will generate generate or
1218 instruction with lfence. -mlfence-before-ret=shl/yes will generate
1219 shl instruction with lfence. -mlfence-before-ret=not will generate
1220 not instruction with lfence. -mlfence-before-ret=none will not
1221 generate lfence, which is the default.
1222 -mx86-used-note=no
1224 -mx86-used-note=yes
1225 These options control whether the assembler should generate
1226 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1227 property notes. The default can be controlled by the
1228 --enable-x86-used-note configure option.
1229 -mevexrcig=rne
1231 -mevexrcig=rd
1232 -mevexrcig=ru
1233 -mevexrcig=rz
1234 These options control how the assembler should encode SAE-only EVEX
1235 instructions. -mevexrcig=rne will encode RC bits of EVEX
1236 instruction with 00, which is the default. -mevexrcig=rd,
1237 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1238 instructions with 01, 10 and 11 RC bits, respectively.
1239 -mamd64
1241 -mintel64
1242 This option specifies that the assembler should accept only AMD64
1243 or Intel64 ISA in 64-bit mode. The default is to accept common,
1244 Intel64 only and AMD64 ISAs.
1245 -O0 | -O | -O1 | -O2 | -Os
1247 Optimize instruction encoding with smaller instruction size. -O
1248 and -O1 encode 64-bit register load instructions with 64-bit
1249 immediate as 32-bit register load instructions with 31-bit or
1250 32-bits immediates, encode 64-bit register clearing instructions
1251 with 32-bit register clearing instructions, encode 256-bit/512-bit
1252 VEX/EVEX vector register clearing instructions with 128-bit VEX
1253 vector register clearing instructions, encode 128-bit/256-bit EVEX
1254 vector register load/store instructions with VEX vector register
1255 load/store instructions, and encode 128-bit/256-bit EVEX packed
1256 integer logical instructions with 128-bit/256-bit VEX packed
1257 integer logical.
1258 -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1260 vector register clearing instructions with 128-bit EVEX vector
1261 register clearing instructions. In 64-bit mode VEX encoded
1262 instructions with commutative source operands will also have their
1263 source operands swapped if this allows using the 2-byte VEX prefix
1264 form instead of the 3-byte one. Certain forms of AND as well as OR
1265 with the same (register) operand specified twice will also be
1266 changed to TEST.
1267 -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1269 64-bit register tests with immediate as 8-bit register test with
1270 immediate. -O0 turns off this optimization.
1271 The following options are available when as is configured for the
1273 Ubicom IP2K series.
1274 -mip2022ext
1276 Specifies that the extended IP2022 instructions are allowed.
1277 -mip2022
1279 Restores the default behaviour, which restricts the permitted
1280 instructions to just the basic IP2022 ones.
1281 The following options are available when as is configured for the
1283 Renesas M32C and M16C processors.
1284 -m32c
1286 Assemble M32C instructions.
1287 -m16c
1289 Assemble M16C instructions (the default).
1290 -relax
1292 Enable support for link-time relaxations.
1293 -h-tick-hex
1295 Support H'00 style hex constants in addition to 0x00 style.
1296 The following options are available when as is configured for the
1298 Renesas M32R (formerly Mitsubishi M32R) series.
1299 --m32rx
1301 Specify which processor in the M32R family is the target. The
1302 default is normally the M32R, but this option changes it to the
1303 M32RX.
1304 --warn-explicit-parallel-conflicts or --Wp
1306 Produce warning messages when questionable parallel constructs are
1307 encountered.
1308 --no-warn-explicit-parallel-conflicts or --Wnp
1310 Do not produce warning messages when questionable parallel
1311 constructs are encountered.
1312 The following options are available when as is configured for the
1314 Motorola 68000 series.
1315 -l Shorten references to undefined symbols, to one word instead of
1317 two.
1318 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1320 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1321 | -m68333 | -m68340 | -mcpu32 | -m5200
1322 Specify what processor in the 68000 family is the target. The
1323 default is normally the 68020, but this can be changed at
1324 configuration time.
1325 -m68881 | -m68882 | -mno-68881 | -mno-68882
1327 The target machine does (or does not) have a floating-point
1328 coprocessor. The default is to assume a coprocessor for 68020,
1329 68030, and cpu32. Although the basic 68000 is not compatible with
1330 the 68881, a combination of the two can be specified, since it's
1331 possible to do emulation of the coprocessor instructions with the
1332 main processor.
1333 -m68851 | -mno-68851
1335 The target machine does (or does not) have a memory-management unit
1336 coprocessor. The default is to assume an MMU for 68020 and up.
1337 The following options are available when as is configured for an Altera
1339 Nios II processor.
1340 -relax-section
1342 Replace identified out-of-range branches with PC-relative "jmp"
1343 sequences when possible. The generated code sequences are suitable
1344 for use in position-independent code, but there is a practical
1345 limit on the extended branch range because of the length of the
1346 sequences. This option is the default.
1347 -relax-all
1349 Replace branch instructions not determinable to be in range and all
1350 call instructions with "jmp" and "callr" sequences (respectively).
1351 This option generates absolute relocations against the target
1352 symbols and is not appropriate for position-independent code.
1353 -no-relax
1355 Do not replace any branches or calls.
1356 -EB Generate big-endian output.
1358 -EL Generate little-endian output. This is the default.
1360 -march=architecture
1362 This option specifies the target architecture. The assembler
1363 issues an error message if an attempt is made to assemble an
1364 instruction which will not execute on the target architecture. The
1365 following architecture names are recognized: "r1", "r2". The
1366 default is "r1".
1367 The following options are available when as is configured for a PRU
1369 processor.
1370 -mlink-relax
1372 Assume that LD would optimize LDI32 instructions by checking the
1373 upper 16 bits of the expression. If they are all zeros, then LD
1374 would shorten the LDI32 instruction to a single LDI. In such case
1375 "as" will output DIFF relocations for diff expressions.
1376 -mno-link-relax
1378 Assume that LD would not optimize LDI32 instructions. As a
1379 consequence, DIFF relocations will not be emitted.
1380 -mno-warn-regname-label
1382 Do not warn if a label name matches a register name. Usually
1383 assembler programmers will want this warning to be emitted. C
1384 compilers may want to turn this off.
1385 The following options are available when as is configured for a MIPS
1387 processor.
1388 -G num
1390 This option sets the largest size of an object that can be
1391 referenced implicitly with the "gp" register. It is only accepted
1392 for targets that use ECOFF format, such as a DECstation running
1393 Ultrix. The default value is 8.
1394 -EB Generate "big endian" format output.
1396 -EL Generate "little endian" format output.
1398 -mips1
1400 -mips2
1401 -mips3
1402 -mips4
1403 -mips5
1404 -mips32
1405 -mips32r2
1406 -mips32r3
1407 -mips32r5
1408 -mips32r6
1409 -mips64
1410 -mips64r2
1411 -mips64r3
1412 -mips64r5
1413 -mips64r6
1414 Generate code for a particular MIPS Instruction Set Architecture
1415 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1416 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1417 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1418 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1419 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1420 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1421 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1422 Release 6 ISA processors, respectively.
1423 -march=cpu
1425 Generate code for a particular MIPS CPU.
1426 -mtune=cpu
1428 Schedule and tune for a particular MIPS CPU.
1429 -mfix7000
1431 -mno-fix7000
1432 Cause nops to be inserted if the read of the destination register
1433 of an mfhi or mflo instruction occurs in the following two
1434 instructions.
1435 -mfix-rm7000
1437 -mno-fix-rm7000
1438 Cause nops to be inserted if a dmult or dmultu instruction is
1439 followed by a load instruction.
1440 -mfix-r5900
1442 -mno-fix-r5900
1443 Do not attempt to schedule the preceding instruction into the delay
1444 slot of a branch instruction placed at the end of a short loop of
1445 six instructions or fewer and always schedule a "nop" instruction
1446 there instead. The short loop bug under certain conditions causes
1447 loops to execute only once or twice, due to a hardware bug in the
1448 R5900 chip.
1449 -mdebug
1451 -no-mdebug
1452 Cause stabs-style debugging output to go into an ECOFF-style
1453 .mdebug section instead of the standard ELF .stabs sections.
1454 -mpdr
1456 -mno-pdr
1457 Control generation of ".pdr" sections.
1458 -mgp32
1460 -mfp32
1461 The register sizes are normally inferred from the ISA and ABI, but
1462 these flags force a certain group of registers to be treated as 32
1463 bits wide at all times. -mgp32 controls the size of general-
1464 purpose registers and -mfp32 controls the size of floating-point
1465 registers.
1466 -mgp64
1468 -mfp64
1469 The register sizes are normally inferred from the ISA and ABI, but
1470 these flags force a certain group of registers to be treated as 64
1471 bits wide at all times. -mgp64 controls the size of general-
1472 purpose registers and -mfp64 controls the size of floating-point
1473 registers.
1474 -mfpxx
1476 The register sizes are normally inferred from the ISA and ABI, but
1477 using this flag in combination with -mabi=32 enables an ABI variant
1478 which will operate correctly with floating-point registers which
1479 are 32 or 64 bits wide.
1480 -modd-spreg
1482 -mno-odd-spreg
1483 Enable use of floating-point operations on odd-numbered single-
1484 precision registers when supported by the ISA. -mfpxx implies
1485 -mno-odd-spreg, otherwise the default is -modd-spreg.
1486 -mips16
1488 -no-mips16
1489 Generate code for the MIPS 16 processor. This is equivalent to
1490 putting ".module mips16" at the start of the assembly file.
1491 -no-mips16 turns off this option.
1492 -mmips16e2
1494 -mno-mips16e2
1495 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1496 equivalent to putting ".module mips16e2" at the start of the
1497 assembly file. -mno-mips16e2 turns off this option.
1498 -mmicromips
1500 -mno-micromips
1501 Generate code for the microMIPS processor. This is equivalent to
1502 putting ".module micromips" at the start of the assembly file.
1503 -mno-micromips turns off this option. This is equivalent to
1504 putting ".module nomicromips" at the start of the assembly file.
1505 -msmartmips
1507 -mno-smartmips
1508 Enables the SmartMIPS extension to the MIPS32 instruction set.
1509 This is equivalent to putting ".module smartmips" at the start of
1510 the assembly file. -mno-smartmips turns off this option.
1511 -mips3d
1513 -no-mips3d
1514 Generate code for the MIPS-3D Application Specific Extension. This
1515 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1516 turns off this option.
1517 -mdmx
1519 -no-mdmx
1520 Generate code for the MDMX Application Specific Extension. This
1521 tells the assembler to accept MDMX instructions. -no-mdmx turns
1522 off this option.
1523 -mdsp
1525 -mno-dsp
1526 Generate code for the DSP Release 1 Application Specific Extension.
1527 This tells the assembler to accept DSP Release 1 instructions.
1528 -mno-dsp turns off this option.
1529 -mdspr2
1531 -mno-dspr2
1532 Generate code for the DSP Release 2 Application Specific Extension.
1533 This option implies -mdsp. This tells the assembler to accept DSP
1534 Release 2 instructions. -mno-dspr2 turns off this option.
1535 -mdspr3
1537 -mno-dspr3
1538 Generate code for the DSP Release 3 Application Specific Extension.
1539 This option implies -mdsp and -mdspr2. This tells the assembler to
1540 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1541 option.
1542 -mmsa
1544 -mno-msa
1545 Generate code for the MIPS SIMD Architecture Extension. This tells
1546 the assembler to accept MSA instructions. -mno-msa turns off this
1547 option.
1548 -mxpa
1550 -mno-xpa
1551 Generate code for the MIPS eXtended Physical Address (XPA)
1552 Extension. This tells the assembler to accept XPA instructions.
1553 -mno-xpa turns off this option.
1554 -mmt
1556 -mno-mt
1557 Generate code for the MT Application Specific Extension. This
1558 tells the assembler to accept MT instructions. -mno-mt turns off
1559 this option.
1560 -mmcu
1562 -mno-mcu
1563 Generate code for the MCU Application Specific Extension. This
1564 tells the assembler to accept MCU instructions. -mno-mcu turns off
1565 this option.
1566 -mcrc
1568 -mno-crc
1569 Generate code for the MIPS cyclic redundancy check (CRC)
1570 Application Specific Extension. This tells the assembler to accept
1571 CRC instructions. -mno-crc turns off this option.
1572 -mginv
1574 -mno-ginv
1575 Generate code for the Global INValidate (GINV) Application Specific
1576 Extension. This tells the assembler to accept GINV instructions.
1577 -mno-ginv turns off this option.
1578 -mloongson-mmi
1580 -mno-loongson-mmi
1581 Generate code for the Loongson MultiMedia extensions Instructions
1582 (MMI) Application Specific Extension. This tells the assembler to
1583 accept MMI instructions. -mno-loongson-mmi turns off this option.
1584 -mloongson-cam
1586 -mno-loongson-cam
1587 Generate code for the Loongson Content Address Memory (CAM)
1588 instructions. This tells the assembler to accept Loongson CAM
1589 instructions. -mno-loongson-cam turns off this option.
1590 -mloongson-ext
1592 -mno-loongson-ext
1593 Generate code for the Loongson EXTensions (EXT) instructions. This
1594 tells the assembler to accept Loongson EXT instructions.
1595 -mno-loongson-ext turns off this option.
1596 -mloongson-ext2
1598 -mno-loongson-ext2
1599 Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1600 This option implies -mloongson-ext. This tells the assembler to
1601 accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off
1602 this option.
1603 -minsn32
1605 -mno-insn32
1606 Only use 32-bit instruction encodings when generating code for the
1607 microMIPS processor. This option inhibits the use of any 16-bit
1608 instructions. This is equivalent to putting ".set insn32" at the
1609 start of the assembly file. -mno-insn32 turns off this option.
1610 This is equivalent to putting ".set noinsn32" at the start of the
1611 assembly file. By default -mno-insn32 is selected, allowing all
1612 instructions to be used.
1613 --construct-floats
1615 --no-construct-floats
1616 The --no-construct-floats option disables the construction of
1617 double width floating point constants by loading the two halves of
1618 the value into the two single width floating point registers that
1619 make up the double width register. By default --construct-floats
1620 is selected, allowing construction of these floating point
1621 constants.
1622 --relax-branch
1624 --no-relax-branch
1625 The --relax-branch option enables the relaxation of out-of-range
1626 branches. By default --no-relax-branch is selected, causing any
1627 out-of-range branches to produce an error.
1628 -mignore-branch-isa
1630 -mno-ignore-branch-isa
1631 Ignore branch checks for invalid transitions between ISA modes.
1632 The semantics of branches does not provide for an ISA mode switch,
1633 so in most cases the ISA mode a branch has been encoded for has to
1634 be the same as the ISA mode of the branch's target label.
1635 Therefore GAS has checks implemented that verify in branch assembly
1636 that the two ISA modes match. -mignore-branch-isa disables these
1637 checks. By default -mno-ignore-branch-isa is selected, causing any
1638 invalid branch requiring a transition between ISA modes to produce
1639 an error.
1640 -mnan=encoding
1642 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1643 (-mnan=legacy) NaN encoding format. The latter is the default.
1644 --emulation=name
1646 This option was formerly used to switch between ELF and ECOFF
1647 output on targets like IRIX 5 that supported both. MIPS ECOFF
1648 support was removed in GAS 2.24, so the option now serves little
1649 purpose. It is retained for backwards compatibility.
1650 The available configuration names are: mipself, mipslelf and
1652 mipsbelf. Choosing mipself now has no effect, since the output is
1653 always ELF. mipslelf and mipsbelf select little- and big-endian
1654 output respectively, but -EL and -EB are now the preferred options
1655 instead.
1656 -nocpp
1658 as ignores this option. It is accepted for compatibility with the
1659 native tools.
1660 --trap
1662 --no-trap
1663 --break
1664 --no-break
1665 Control how to deal with multiplication overflow and division by
1666 zero. --trap or --no-break (which are synonyms) take a trap
1667 exception (and only work for Instruction Set Architecture level 2
1668 and higher); --break or --no-trap (also synonyms, and the default)
1669 take a break exception.
1670 -n When this option is used, as will issue a warning every time it
1672 generates a nop instruction from a macro.
1673 The following options are available when as is configured for a Meta
1675 processor.
1676 "-mcpu=metac11"
1678 Generate code for Meta 1.1.
1679 "-mcpu=metac12"
1681 Generate code for Meta 1.2.
1682 "-mcpu=metac21"
1684 Generate code for Meta 2.1.
1685 "-mfpu=metac21"
1687 Allow code to use FPU hardware of Meta 2.1.
1688 See the info pages for documentation of the MMIX-specific options.
1690 The following options are available when as is configured for a NDS32
1692 processor.
1693 "-O1"
1695 Optimize for performance.
1696 "-Os"
1698 Optimize for space.
1699 "-EL"
1701 Produce little endian data output.
1702 "-EB"
1704 Produce little endian data output.
1705 "-mpic"
1707 Generate PIC.
1708 "-mno-fp-as-gp-relax"
1710 Suppress fp-as-gp relaxation for this file.
1711 "-mb2bb-relax"
1713 Back-to-back branch optimization.
1714 "-mno-all-relax"
1716 Suppress all relaxation for this file.
1717 "-march=<arch name>"
1719 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1720 v3f, v3s, v2, v2j, v2f, v2s.
1721 "-mbaseline=<baseline>"
1723 Assemble for baseline <baseline> which could be v2, v3, v3m.
1724 "-mfpu-freg=FREG"
1726 Specify a FPU configuration.
1727 "0 8 SP / 4 DP registers"
1729 "1 16 SP / 8 DP registers"
1730 "2 32 SP / 16 DP registers"
1731 "3 32 SP / 32 DP registers"
1732 "-mabi=abi"
1733 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1734 "-m[no-]mac"
1736 Enable/Disable Multiply instructions support.
1737 "-m[no-]div"
1739 Enable/Disable Divide instructions support.
1740 "-m[no-]16bit-ext"
1742 Enable/Disable 16-bit extension
1743 "-m[no-]dx-regs"
1745 Enable/Disable d0/d1 registers
1746 "-m[no-]perf-ext"
1748 Enable/Disable Performance extension
1749 "-m[no-]perf2-ext"
1751 Enable/Disable Performance extension 2
1752 "-m[no-]string-ext"
1754 Enable/Disable String extension
1755 "-m[no-]reduced-regs"
1757 Enable/Disable Reduced Register configuration (GPR16) option
1758 "-m[no-]audio-isa-ext"
1760 Enable/Disable AUDIO ISA extension
1761 "-m[no-]fpu-sp-ext"
1763 Enable/Disable FPU SP extension
1764 "-m[no-]fpu-dp-ext"
1766 Enable/Disable FPU DP extension
1767 "-m[no-]fpu-fma"
1769 Enable/Disable FPU fused-multiply-add instructions
1770 "-mall-ext"
1772 Turn on all extensions and instructions support
1773 The following options are available when as is configured for a PowerPC
1775 processor.
1776 -a32
1778 Generate ELF32 or XCOFF32.
1779 -a64
1781 Generate ELF64 or XCOFF64.
1782 -K PIC
1784 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1785 -mpwrx | -mpwr2
1787 Generate code for POWER/2 (RIOS2).
1788 -mpwr
1790 Generate code for POWER (RIOS1)
1791 -m601
1793 Generate code for PowerPC 601.
1794 -mppc, -mppc32, -m603, -m604
1796 Generate code for PowerPC 603/604.
1797 -m403, -m405
1799 Generate code for PowerPC 403/405.
1800 -m440
1802 Generate code for PowerPC 440. BookE and some 405 instructions.
1803 -m464
1805 Generate code for PowerPC 464.
1806 -m476
1808 Generate code for PowerPC 476.
1809 -m7400, -m7410, -m7450, -m7455
1811 Generate code for PowerPC 7400/7410/7450/7455.
1812 -m750cl, -mgekko, -mbroadway
1814 Generate code for PowerPC 750CL/Gekko/Broadway.
1815 -m821, -m850, -m860
1817 Generate code for PowerPC 821/850/860.
1818 -mppc64, -m620
1820 Generate code for PowerPC 620/625/630.
1821 -me500, -me500x2
1823 Generate code for Motorola e500 core complex.
1824 -me500mc
1826 Generate code for Freescale e500mc core complex.
1827 -me500mc64
1829 Generate code for Freescale e500mc64 core complex.
1830 -me5500
1832 Generate code for Freescale e5500 core complex.
1833 -me6500
1835 Generate code for Freescale e6500 core complex.
1836 -mspe
1838 Generate code for Motorola SPE instructions.
1839 -mspe2
1841 Generate code for Freescale SPE2 instructions.
1842 -mtitan
1844 Generate code for AppliedMicro Titan core complex.
1845 -mppc64bridge
1847 Generate code for PowerPC 64, including bridge insns.
1848 -mbooke
1850 Generate code for 32-bit BookE.
1851 -ma2
1853 Generate code for A2 architecture.
1854 -me300
1856 Generate code for PowerPC e300 family.
1857 -maltivec
1859 Generate code for processors with AltiVec instructions.
1860 -mvle
1862 Generate code for Freescale PowerPC VLE instructions.
1863 -mvsx
1865 Generate code for processors with Vector-Scalar (VSX) instructions.
1866 -mhtm
1868 Generate code for processors with Hardware Transactional Memory
1869 instructions.
1870 -mpower4, -mpwr4
1872 Generate code for Power4 architecture.
1873 -mpower5, -mpwr5, -mpwr5x
1875 Generate code for Power5 architecture.
1876 -mpower6, -mpwr6
1878 Generate code for Power6 architecture.
1879 -mpower7, -mpwr7
1881 Generate code for Power7 architecture.
1882 -mpower8, -mpwr8
1884 Generate code for Power8 architecture.
1885 -mpower9, -mpwr9
1887 Generate code for Power9 architecture.
1888 -mpower10, -mpwr10
1890 Generate code for Power10 architecture.
1891 -mcell
1893 -mcell
1894 Generate code for Cell Broadband Engine architecture.
1895 -mcom
1897 Generate code Power/PowerPC common instructions.
1898 -many
1900 Generate code for any architecture (PWR/PWRX/PPC).
1901 -mregnames
1903 Allow symbolic names for registers.
1904 -mno-regnames
1906 Do not allow symbolic names for registers.
1907 -mrelocatable
1909 Support for GCC's -mrelocatable option.
1910 -mrelocatable-lib
1912 Support for GCC's -mrelocatable-lib option.
1913 -memb
1915 Set PPC_EMB bit in ELF flags.
1916 -mlittle, -mlittle-endian, -le
1918 Generate code for a little endian machine.
1919 -mbig, -mbig-endian, -be
1921 Generate code for a big endian machine.
1922 -msolaris
1924 Generate code for Solaris.
1925 -mno-solaris
1927 Do not generate code for Solaris.
1928 -nops=count
1930 If an alignment directive inserts more than count nops, put a
1931 branch at the beginning to skip execution of the nops.
1932 The following options are available when as is configured for a RISC-V
1934 processor.
1935 -fpic
1937 -fPIC
1938 Generate position-independent code
1939 -fno-pic
1941 Don't generate position-independent code (default)
1942 -march=ISA
1944 Select the base isa, as specified by ISA. For example
1945 -march=rv32ima. If this option and the architecture attributes
1946 aren't set, then assembler will check the default configure setting
1947 --with-arch=ISA.
1948 -misa-spec=ISAspec
1950 Select the default isa spec version. If the version of ISA isn't
1951 set by -march, then assembler helps to set the version according to
1952 the default chosen spec. If this option isn't set, then assembler
1953 will check the default configure setting --with-isa-spec=ISAspec.
1954 -mpriv-spec=PRIVspec
1956 Select the privileged spec version. We can decide whether the CSR
1957 is valid or not according to the chosen spec. If this option and
1958 the privilege attributes aren't set, then assembler will check the
1959 default configure setting --with-priv-spec=PRIVspec.
1960 -mabi=ABI
1962 Selects the ABI, which is either "ilp32" or "lp64", optionally
1963 followed by "f", "d", or "q" to indicate single-precision, double-
1964 precision, or quad-precision floating-point calling convention, or
1965 none to indicate the soft-float calling convention. Also, "ilp32"
1966 can optionally be followed by "e" to indicate the RVE ABI, which is
1967 always soft-float.
1968 -mrelax
1970 Take advantage of linker relaxations to reduce the number of
1971 instructions required to materialize symbol addresses. (default)
1972 -mno-relax
1974 Don't do linker relaxations.
1975 -march-attr
1977 Generate the default contents for the riscv elf attribute section
1978 if the .attribute directives are not set. This section is used to
1979 record the information that a linker or runtime loader needs to
1980 check compatibility. This information includes ISA string, stack
1981 alignment requirement, unaligned memory accesses, and the major,
1982 minor and revision version of privileged specification.
1983 -mno-arch-attr
1985 Don't generate the default riscv elf attribute section if the
1986 .attribute directives are not set.
1987 -mcsr-check
1989 Enable the CSR checking for the ISA-dependent CRS and the read-only
1990 CSR. The ISA-dependent CSR are only valid when the specific ISA is
1991 set. The read-only CSR can not be written by the CSR instructions.
1992 -mno-csr-check
1994 Don't do CSR checking.
1995 -mlittle-endian
1997 Generate code for a little endian machine.
1998 -mbig-endian
2000 Generate code for a big endian machine.
2001 See the info pages for documentation of the RX-specific options.
2003 The following options are available when as is configured for the s390
2005 processor family.
2006 -m31
2008 -m64
2009 Select the word size, either 31/32 bits or 64 bits.
2010 -mesa
2012 -mzarch
2013 Select the architecture mode, either the Enterprise System
2014 Architecture (esa) or the z/Architecture mode (zarch).
2015 -march=processor
2017 Specify which s390 processor variant is the target, g5 (or arch3),
2018 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2019 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2020 z14 (or arch12), or z15 (or arch13).
2021 -mregnames
2023 -mno-regnames
2024 Allow or disallow symbolic names for registers.
2025 -mwarn-areg-zero
2027 Warn whenever the operand for a base or index register has been
2028 specified but evaluates to zero.
2029 The following options are available when as is configured for a
2031 TMS320C6000 processor.
2032 -march=arch
2034 Enable (only) instructions from architecture arch. By default, all
2035 instructions are permitted.
2036 The following values of arch are accepted: "c62x", "c64x", "c64x+",
2038 "c67x", "c67x+", "c674x".
2039 -mdsbt
2041 -mno-dsbt
2042 The -mdsbt option causes the assembler to generate the
2043 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2044 code is using DSBT addressing. The -mno-dsbt option, the default,
2045 causes the tag to have a value of 0, indicating that the code does
2046 not use DSBT addressing. The linker will emit a warning if objects
2047 of different type (DSBT and non-DSBT) are linked together.
2048 -mpid=no
2050 -mpid=near
2051 -mpid=far
2052 The -mpid= option causes the assembler to generate the
2053 "Tag_ABI_PID" attribute with a value indicating the form of data
2054 addressing used by the code. -mpid=no, the default, indicates
2055 position-dependent data addressing, -mpid=near indicates position-
2056 independent addressing with GOT accesses using near DP addressing,
2057 and -mpid=far indicates position-independent addressing with GOT
2058 accesses using far DP addressing. The linker will emit a warning
2059 if objects built with different settings of this option are linked
2060 together.
2061 -mpic
2063 -mno-pic
2064 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2065 attribute with a value of 1, indicating that the code is using
2066 position-independent code addressing, The "-mno-pic" option, the
2067 default, causes the tag to have a value of 0, indicating position-
2068 dependent code addressing. The linker will emit a warning if
2069 objects of different type (position-dependent and position-
2070 independent) are linked together.
2071 -mbig-endian
2073 -mlittle-endian
2074 Generate code for the specified endianness. The default is little-
2075 endian.
2076 The following options are available when as is configured for a TILE-Gx
2078 processor.
2079 -m32 | -m64
2081 Select the word size, either 32 bits or 64 bits.
2082 -EB | -EL
2084 Select the endianness, either big-endian (-EB) or little-endian
2085 (-EL).
2086 The following option is available when as is configured for a Visium
2088 processor.
2089 -mtune=arch
2091 This option specifies the target architecture. If an attempt is
2092 made to assemble an instruction that will not execute on the target
2093 architecture, the assembler will issue an error message.
2094 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2096 The following options are available when as is configured for an Xtensa
2098 processor.
2099 --text-section-literals | --no-text-section-literals
2101 Control the treatment of literal pools. The default is
2102 --no-text-section-literals, which places literals in separate
2103 sections in the output file. This allows the literal pool to be
2104 placed in a data RAM/ROM. With --text-section-literals, the
2105 literals are interspersed in the text section in order to keep them
2106 as close as possible to their references. This may be necessary
2107 for large assembly files, where the literals would otherwise be out
2108 of range of the "L32R" instructions in the text section. Literals
2109 are grouped into pools following ".literal_position" directives or
2110 preceding "ENTRY" instructions. These options only affect literals
2111 referenced via PC-relative "L32R" instructions; literals for
2112 absolute mode "L32R" instructions are handled separately.
2113 --auto-litpools | --no-auto-litpools
2115 Control the treatment of literal pools. The default is
2116 --no-auto-litpools, which in the absence of --text-section-literals
2117 places literals in separate sections in the output file. This
2118 allows the literal pool to be placed in a data RAM/ROM. With
2119 --auto-litpools, the literals are interspersed in the text section
2120 in order to keep them as close as possible to their references,
2121 explicit ".literal_position" directives are not required. This may
2122 be necessary for very large functions, where single literal pool at
2123 the beginning of the function may not be reachable by "L32R"
2124 instructions at the end. These options only affect literals
2125 referenced via PC-relative "L32R" instructions; literals for
2126 absolute mode "L32R" instructions are handled separately. When
2127 used together with --text-section-literals, --auto-litpools takes
2128 precedence.
2129 --absolute-literals | --no-absolute-literals
2131 Indicate to the assembler whether "L32R" instructions use absolute
2132 or PC-relative addressing. If the processor includes the absolute
2133 addressing option, the default is to use absolute "L32R"
2134 relocations. Otherwise, only the PC-relative "L32R" relocations
2135 can be used.
2136 --target-align | --no-target-align
2138 Enable or disable automatic alignment to reduce branch penalties at
2139 some expense in code size. This optimization is enabled by
2140 default. Note that the assembler will always align instructions
2141 like "LOOP" that have fixed alignment requirements.
2142 --longcalls | --no-longcalls
2144 Enable or disable transformation of call instructions to allow
2145 calls across a greater range of addresses. This option should be
2146 used when call targets can potentially be out of range. It may
2147 degrade both code size and performance, but the linker can
2148 generally optimize away the unnecessary overhead when a call ends
2149 up within range. The default is --no-longcalls.
2150 --transform | --no-transform
2152 Enable or disable all assembler transformations of Xtensa
2153 instructions, including both relaxation and optimization. The
2154 default is --transform; --no-transform should only be used in the
2155 rare cases when the instructions must be exactly as specified in
2156 the assembly source. Using --no-transform causes out of range
2157 instruction operands to be errors.
2158 --rename-section oldname=newname
2160 Rename the oldname section to newname. This option can be used
2161 multiple times to rename multiple sections.
2162 --trampolines | --no-trampolines
2164 Enable or disable transformation of jump instructions to allow
2165 jumps across a greater range of addresses. This option should be
2166 used when jump targets can potentially be out of range. In the
2167 absence of such jumps this option does not affect code size or
2168 performance. The default is --trampolines.
2169 --abi-windowed | --abi-call0
2171 Choose ABI tag written to the ".xtensa.info" section. ABI tag
2172 indicates ABI of the assembly code. A warning is issued by the
2173 linker on an attempt to link object files with inconsistent ABI
2174 tags. Default ABI is chosen by the Xtensa core configuration.
2175 The following options are available when as is configured for an Z80
2177 processor.
2178 @chapter Z80 Dependent Features
2180 Command-line Options
2182 -march=CPU[-EXT...][+EXT...]
2183 This option specifies the target processor. The assembler will
2184 issue an error message if an attempt is made to assemble an
2185 instruction which will not execute on the target processor. The
2186 following processor names are recognized: "z80", "z180", "ez80",
2187 "gbz80", "z80n", "r800". In addition to the basic instruction set,
2188 the assembler can be told to accept some extention mnemonics. For
2189 example, "-march=z180+sli+infc" extends z180 with SLI instructions
2190 and IN F,(C). The following extentions are currently supported:
2191 "full" (all known instructions), "adl" (ADL CPU mode by default,
2192 eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2193 (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2194 "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2195 "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2196 (C),0). Note that rather than extending a basic instruction set,
2197 the extention mnemonics starting with "-" revoke the respective
2198 functionality: "-march=z80-full+xyhl" first removes all default
2199 extentions and adds support for index registers halves only.
2200 If this option is not specified then "-march=z80+xyhl+infc" is
2202 assumed.
2203 -local-prefix=prefix
2205 Mark all labels with specified prefix as local. But such label can
2206 be marked global explicitly in the code. This option do not change
2207 default local label prefix ".L", it is just adds new one.
2208 -colonless
2210 Accept colonless labels. All symbols at line begin are treated as
2211 labels.
2212 -sdcc
2214 Accept assembler code produced by SDCC.
2215 -fp-s=FORMAT
2217 Single precision floating point numbers format. Default: ieee754
2218 (32 bit).
2219 -fp-d=FORMAT
2221 Double precision floating point numbers format. Default: ieee754
2222 (64 bit).
2223
2225 gcc(1), ld(1), and the Info entries for binutils and ld.
2226
2228 Copyright (c) 1991-2021 Free Software Foundation, Inc.
2229 Permission is granted to copy, distribute and/or modify this document
2231 under the terms of the GNU Free Documentation License, Version 1.3 or
2232 any later version published by the Free Software Foundation; with no
2233 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2234 Texts. A copy of the license is included in the section entitled "GNU
2235 Free Documentation License".
2236binutils-2.37 2021-09-16 AS(1)